Lines Matching refs:AHB1SMENR

3157 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE()         SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SME…
3159 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE()         SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSME…
3161 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE()           SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
3163 #define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE()           SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN)
3165 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()          SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
3167 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()            SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
3170 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE()           SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN)
3173 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE()            SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
3175 #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE()         SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSME…
3178 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()          SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
3182 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()         SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSME…
3186 #define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE()          SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN)
3190 #define __HAL_RCC_DCACHE2_CLK_SLEEP_ENABLE()        SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SM…
3193 #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE()          SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN)
3195 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()        SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSM…
3197 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE()         SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESME…
3199 #define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE()        SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SM…
3201 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()          SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
3203 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE()        CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1S…
3205 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE()        CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICS…
3207 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE()          CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSME…
3209 #define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE()          CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SME…
3211 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()         CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSM…
3213 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()           CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
3216 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE()          CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSME…
3219 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE()           CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
3221 #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE()        CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGS…
3224 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()         CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSM…
3228 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE()        CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUS…
3232 #define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE()         CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSM…
3236 #define __HAL_RCC_DCACHE2_CLK_SLEEP_DISABLE()       CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2…
3239 #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE()         CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SM…
3241 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()       CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAM…
3243 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE()        CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHES…
3245 #define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE()       CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1…
3247 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()         CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SM…