502   uint32_t tmpccer;  in LL_TIM_ENCODER_Init()  local
523   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
538   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_ENCODER_Init()
539   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);  in LL_TIM_ENCODER_Init()
540   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);  in LL_TIM_ENCODER_Init()
541   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
550   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
596   uint32_t tmpccer;  in LL_TIM_HALLSENSOR_Init()  local
615   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
642   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_HALLSENSOR_Init()
643   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);  in LL_TIM_HALLSENSOR_Init()
644   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
656   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
777   uint32_t tmpccer;  in OC1Config()  local
790   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
805   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);  in OC1Config()
808   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);  in OC1Config()
818     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);  in OC1Config()
821     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);  in OC1Config()
840   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
856   uint32_t tmpccer;  in OC2Config()  local
869   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
884   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);  in OC2Config()
887   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);  in OC2Config()
897     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);  in OC2Config()
900     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);  in OC2Config()
919   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
935   uint32_t tmpccer;  in OC3Config()  local
948   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
963   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);  in OC3Config()
966   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);  in OC3Config()
976     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);  in OC3Config()
979     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);  in OC3Config()
998   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1014   uint32_t tmpccer;  in OC4Config()  local
1027   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1042   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);  in OC4Config()
1045   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);  in OC4Config()
1065   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1081   uint32_t tmpccer;  in OC5Config()  local
1095   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1104   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);  in OC5Config()
1107   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);  in OC5Config()
1126   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1142   uint32_t tmpccer;  in OC6Config()  local
1156   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1165   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);  in OC6Config()
1168   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);  in OC6Config()
1186   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()