517   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
523   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
550   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
606   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
615   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
656   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
787   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
790   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
840   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
866   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
869   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
919   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
945   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
948   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
998   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1024   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1027   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1065   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1092   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1095   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1126   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1153   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1156   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1186   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1209   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1217   MODIFY_REG(TIMx->CCER,  in IC1Config()
1242   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1250   MODIFY_REG(TIMx->CCER,  in IC2Config()
1275   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1283   MODIFY_REG(TIMx->CCER,  in IC3Config()
1308   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1316   MODIFY_REG(TIMx->CCER,  in IC4Config()