Lines Matching refs:htim
235 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
277 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Init() argument
280 if (htim == NULL) in HAL_TIM_Base_Init()
286 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Init()
287 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_Base_Init()
288 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_Base_Init()
289 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_Base_Init()
290 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_Base_Init()
292 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_Base_Init()
295 htim->Lock = HAL_UNLOCKED; in HAL_TIM_Base_Init()
299 TIM_ResetCallback(htim); in HAL_TIM_Base_Init()
301 if (htim->Base_MspInitCallback == NULL) in HAL_TIM_Base_Init()
303 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_Base_Init()
306 htim->Base_MspInitCallback(htim); in HAL_TIM_Base_Init()
309 HAL_TIM_Base_MspInit(htim); in HAL_TIM_Base_Init()
314 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Init()
317 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_Base_Init()
320 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_Base_Init()
323 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Base_Init()
324 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Base_Init()
327 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Init()
337 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_DeInit() argument
340 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_DeInit()
342 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_DeInit()
345 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_DeInit()
348 if (htim->Base_MspDeInitCallback == NULL) in HAL_TIM_Base_DeInit()
350 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_Base_DeInit()
353 htim->Base_MspDeInitCallback(htim); in HAL_TIM_Base_DeInit()
356 HAL_TIM_Base_MspDeInit(htim); in HAL_TIM_Base_DeInit()
360 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_Base_DeInit()
363 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Base_DeInit()
364 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Base_DeInit()
367 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_Base_DeInit()
370 __HAL_UNLOCK(htim); in HAL_TIM_Base_DeInit()
380 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_MspInit() argument
383 UNUSED(htim); in HAL_TIM_Base_MspInit()
395 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_MspDeInit() argument
398 UNUSED(htim); in HAL_TIM_Base_MspDeInit()
411 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Start() argument
416 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start()
419 if (htim->State != HAL_TIM_STATE_READY) in HAL_TIM_Base_Start()
425 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start()
428 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start()
430 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start()
433 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start()
438 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start()
450 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop() argument
453 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop()
456 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop()
459 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop()
470 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Start_IT() argument
475 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start_IT()
478 if (htim->State != HAL_TIM_STATE_READY) in HAL_TIM_Base_Start_IT()
484 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start_IT()
487 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); in HAL_TIM_Base_Start_IT()
490 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start_IT()
492 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start_IT()
495 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_IT()
500 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_IT()
512 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop_IT() argument
515 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop_IT()
518 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); in HAL_TIM_Base_Stop_IT()
521 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop_IT()
524 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop_IT()
537 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t L… in HAL_TIM_Base_Start_DMA() argument
542 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start_DMA()
545 if (htim->State == HAL_TIM_STATE_BUSY) in HAL_TIM_Base_Start_DMA()
549 else if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_Base_Start_DMA()
557 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start_DMA()
566 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_Base_Start_DMA()
567 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_Base_Start_DMA()
570 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Base_Start_DMA()
573 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->AR… in HAL_TIM_Base_Start_DMA()
581 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); in HAL_TIM_Base_Start_DMA()
584 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start_DMA()
586 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start_DMA()
589 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_DMA()
594 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_DMA()
606 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop_DMA() argument
609 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop_DMA()
612 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); in HAL_TIM_Base_Stop_DMA()
614 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_Base_Stop_DMA()
617 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop_DMA()
620 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop_DMA()
661 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) in HAL_TIM_OC_Init() argument
664 if (htim == NULL) in HAL_TIM_OC_Init()
670 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OC_Init()
671 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_OC_Init()
672 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_OC_Init()
673 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_OC_Init()
674 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_OC_Init()
676 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_OC_Init()
679 htim->Lock = HAL_UNLOCKED; in HAL_TIM_OC_Init()
683 TIM_ResetCallback(htim); in HAL_TIM_OC_Init()
685 if (htim->OC_MspInitCallback == NULL) in HAL_TIM_OC_Init()
687 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_OC_Init()
690 htim->OC_MspInitCallback(htim); in HAL_TIM_OC_Init()
693 HAL_TIM_OC_MspInit(htim); in HAL_TIM_OC_Init()
698 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OC_Init()
701 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_OC_Init()
704 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_OC_Init()
707 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Init()
708 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Init()
711 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OC_Init()
721 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_DeInit() argument
724 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OC_DeInit()
726 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OC_DeInit()
729 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_DeInit()
732 if (htim->OC_MspDeInitCallback == NULL) in HAL_TIM_OC_DeInit()
734 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_OC_DeInit()
737 htim->OC_MspDeInitCallback(htim); in HAL_TIM_OC_DeInit()
740 HAL_TIM_OC_MspDeInit(htim); in HAL_TIM_OC_DeInit()
744 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_OC_DeInit()
747 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OC_DeInit()
748 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OC_DeInit()
751 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_OC_DeInit()
754 __HAL_UNLOCK(htim); in HAL_TIM_OC_DeInit()
764 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_MspInit() argument
767 UNUSED(htim); in HAL_TIM_OC_MspInit()
779 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_MspDeInit() argument
782 UNUSED(htim); in HAL_TIM_OC_MspDeInit()
802 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Start() argument
807 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_OC_Start()
810 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start()
816 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start()
819 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start()
821 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start()
824 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start()
828 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start()
830 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start()
833 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start()
838 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start()
858 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop() argument
861 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_OC_Stop()
864 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop()
866 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop()
869 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop()
873 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop()
876 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop()
893 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Start_IT() argument
899 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Start_IT()
902 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start_IT()
908 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start_IT()
915 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OC_Start_IT()
922 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OC_Start_IT()
929 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_OC_Start_IT()
936 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_OC_Start_IT()
948 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start_IT()
950 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start_IT()
953 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start_IT()
957 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start_IT()
959 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start_IT()
962 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_IT()
967 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_IT()
986 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop_IT() argument
991 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Stop_IT()
998 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OC_Stop_IT()
1005 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OC_Stop_IT()
1012 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_OC_Stop_IT()
1019 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_OC_Stop_IT()
1031 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop_IT()
1033 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop_IT()
1036 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop_IT()
1040 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop_IT()
1043 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop_IT()
1063 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *p… in HAL_TIM_OC_Start_DMA() argument
1070 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Start_DMA()
1073 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) in HAL_TIM_OC_Start_DMA()
1077 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start_DMA()
1085 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start_DMA()
1098 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1099 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1102 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1105 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, in HAL_TIM_OC_Start_DMA()
1113 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_OC_Start_DMA()
1120 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1121 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1124 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1127 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, in HAL_TIM_OC_Start_DMA()
1135 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_OC_Start_DMA()
1142 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1143 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1146 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1149 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, in HAL_TIM_OC_Start_DMA()
1156 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_OC_Start_DMA()
1163 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1164 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1167 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1170 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, in HAL_TIM_OC_Start_DMA()
1177 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_OC_Start_DMA()
1189 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start_DMA()
1191 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start_DMA()
1194 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1198 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start_DMA()
1200 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start_DMA()
1203 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1208 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1227 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop_DMA() argument
1232 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Stop_DMA()
1239 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_OC_Stop_DMA()
1240 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_OC_Stop_DMA()
1247 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_OC_Stop_DMA()
1248 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_OC_Stop_DMA()
1255 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_OC_Stop_DMA()
1256 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_OC_Stop_DMA()
1263 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_OC_Stop_DMA()
1264 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_OC_Stop_DMA()
1276 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop_DMA()
1278 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop_DMA()
1281 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop_DMA()
1285 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop_DMA()
1288 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop_DMA()
1330 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_Init() argument
1333 if (htim == NULL) in HAL_TIM_PWM_Init()
1339 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_PWM_Init()
1340 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_PWM_Init()
1341 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_PWM_Init()
1342 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_PWM_Init()
1343 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_PWM_Init()
1345 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_PWM_Init()
1348 htim->Lock = HAL_UNLOCKED; in HAL_TIM_PWM_Init()
1352 TIM_ResetCallback(htim); in HAL_TIM_PWM_Init()
1354 if (htim->PWM_MspInitCallback == NULL) in HAL_TIM_PWM_Init()
1356 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_PWM_Init()
1359 htim->PWM_MspInitCallback(htim); in HAL_TIM_PWM_Init()
1362 HAL_TIM_PWM_MspInit(htim); in HAL_TIM_PWM_Init()
1367 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_PWM_Init()
1370 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_PWM_Init()
1373 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_PWM_Init()
1376 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Init()
1377 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Init()
1380 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_PWM_Init()
1390 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_DeInit() argument
1393 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_PWM_DeInit()
1395 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_PWM_DeInit()
1398 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_DeInit()
1401 if (htim->PWM_MspDeInitCallback == NULL) in HAL_TIM_PWM_DeInit()
1403 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_PWM_DeInit()
1406 htim->PWM_MspDeInitCallback(htim); in HAL_TIM_PWM_DeInit()
1409 HAL_TIM_PWM_MspDeInit(htim); in HAL_TIM_PWM_DeInit()
1413 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_PWM_DeInit()
1416 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_PWM_DeInit()
1417 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_PWM_DeInit()
1420 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_PWM_DeInit()
1423 __HAL_UNLOCK(htim); in HAL_TIM_PWM_DeInit()
1433 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_MspInit() argument
1436 UNUSED(htim); in HAL_TIM_PWM_MspInit()
1448 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_MspDeInit() argument
1451 UNUSED(htim); in HAL_TIM_PWM_MspDeInit()
1471 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Start() argument
1476 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_PWM_Start()
1479 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start()
1485 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start()
1488 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start()
1490 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start()
1493 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start()
1497 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start()
1499 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start()
1502 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start()
1507 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start()
1527 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop() argument
1530 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_PWM_Stop()
1533 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop()
1535 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop()
1538 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop()
1542 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop()
1545 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop()
1562 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Start_IT() argument
1568 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Start_IT()
1571 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start_IT()
1577 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start_IT()
1584 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_PWM_Start_IT()
1591 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_PWM_Start_IT()
1598 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_PWM_Start_IT()
1605 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_PWM_Start_IT()
1617 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start_IT()
1619 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start_IT()
1622 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1626 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start_IT()
1628 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start_IT()
1631 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1636 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1655 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop_IT() argument
1660 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Stop_IT()
1667 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_PWM_Stop_IT()
1674 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_PWM_Stop_IT()
1681 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_PWM_Stop_IT()
1688 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_PWM_Stop_IT()
1700 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop_IT()
1702 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop_IT()
1705 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop_IT()
1709 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop_IT()
1712 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop_IT()
1732 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *… in HAL_TIM_PWM_Start_DMA() argument
1739 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Start_DMA()
1742 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) in HAL_TIM_PWM_Start_DMA()
1746 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start_DMA()
1754 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start_DMA()
1767 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1768 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1771 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1774 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, in HAL_TIM_PWM_Start_DMA()
1782 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_PWM_Start_DMA()
1789 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1790 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1793 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1796 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, in HAL_TIM_PWM_Start_DMA()
1803 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_PWM_Start_DMA()
1810 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1811 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1814 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1817 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, in HAL_TIM_PWM_Start_DMA()
1824 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_PWM_Start_DMA()
1831 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1832 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1835 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1838 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, in HAL_TIM_PWM_Start_DMA()
1845 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_PWM_Start_DMA()
1857 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start_DMA()
1859 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start_DMA()
1862 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1866 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start_DMA()
1868 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start_DMA()
1871 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1876 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1895 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop_DMA() argument
1900 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Stop_DMA()
1907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_PWM_Stop_DMA()
1908 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_PWM_Stop_DMA()
1915 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_PWM_Stop_DMA()
1916 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_PWM_Stop_DMA()
1923 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_PWM_Stop_DMA()
1924 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_PWM_Stop_DMA()
1931 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_PWM_Stop_DMA()
1932 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_PWM_Stop_DMA()
1944 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop_DMA()
1946 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop_DMA()
1949 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop_DMA()
1953 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop_DMA()
1956 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop_DMA()
1998 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) in HAL_TIM_IC_Init() argument
2001 if (htim == NULL) in HAL_TIM_IC_Init()
2007 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_IC_Init()
2008 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_IC_Init()
2009 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_IC_Init()
2010 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_IC_Init()
2011 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_IC_Init()
2013 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_IC_Init()
2016 htim->Lock = HAL_UNLOCKED; in HAL_TIM_IC_Init()
2020 TIM_ResetCallback(htim); in HAL_TIM_IC_Init()
2022 if (htim->IC_MspInitCallback == NULL) in HAL_TIM_IC_Init()
2024 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_IC_Init()
2027 htim->IC_MspInitCallback(htim); in HAL_TIM_IC_Init()
2030 HAL_TIM_IC_MspInit(htim); in HAL_TIM_IC_Init()
2035 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_IC_Init()
2038 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_IC_Init()
2041 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_IC_Init()
2044 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Init()
2045 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Init()
2048 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_IC_Init()
2058 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_DeInit() argument
2061 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_IC_DeInit()
2063 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_IC_DeInit()
2066 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_DeInit()
2069 if (htim->IC_MspDeInitCallback == NULL) in HAL_TIM_IC_DeInit()
2071 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_IC_DeInit()
2074 htim->IC_MspDeInitCallback(htim); in HAL_TIM_IC_DeInit()
2077 HAL_TIM_IC_MspDeInit(htim); in HAL_TIM_IC_DeInit()
2081 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_IC_DeInit()
2084 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_IC_DeInit()
2085 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_IC_DeInit()
2088 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_IC_DeInit()
2091 __HAL_UNLOCK(htim); in HAL_TIM_IC_DeInit()
2101 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_MspInit() argument
2104 UNUSED(htim); in HAL_TIM_IC_MspInit()
2116 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_MspDeInit() argument
2119 UNUSED(htim); in HAL_TIM_IC_MspDeInit()
2137 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Start() argument
2140 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start()
2141 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start()
2144 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start()
2154 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start()
2155 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start()
2158 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start()
2161 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start()
2163 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start()
2166 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start()
2171 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start()
2189 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop() argument
2192 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop()
2195 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop()
2198 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop()
2201 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop()
2202 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop()
2219 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Start_IT() argument
2224 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_IT()
2225 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_IT()
2228 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start_IT()
2238 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_IT()
2239 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_IT()
2246 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_IC_Start_IT()
2253 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_IC_Start_IT()
2260 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_IC_Start_IT()
2267 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_IC_Start_IT()
2279 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start_IT()
2282 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start_IT()
2284 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start_IT()
2287 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_IT()
2292 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_IT()
2311 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop_IT() argument
2316 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop_IT()
2323 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_IC_Stop_IT()
2330 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_IC_Stop_IT()
2337 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_IC_Stop_IT()
2344 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_IC_Stop_IT()
2356 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop_IT()
2359 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop_IT()
2362 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_IT()
2363 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_IT()
2383 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, … in HAL_TIM_IC_Start_DMA() argument
2388 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_DMA()
2389 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_DMA()
2392 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start_DMA()
2393 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); in HAL_TIM_IC_Start_DMA()
2410 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_DMA()
2411 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_DMA()
2420 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start_DMA()
2427 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2428 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2431 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2434 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2441 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_IC_Start_DMA()
2448 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2449 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2452 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2455 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2462 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_IC_Start_DMA()
2469 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2470 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2473 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2476 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2483 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_IC_Start_DMA()
2490 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2491 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2494 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2497 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2504 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_IC_Start_DMA()
2514 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start_DMA()
2516 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start_DMA()
2519 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_DMA()
2524 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_DMA()
2542 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop_DMA() argument
2547 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop_DMA()
2548 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); in HAL_TIM_IC_Stop_DMA()
2551 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop_DMA()
2558 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_IC_Stop_DMA()
2559 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_IC_Stop_DMA()
2566 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_IC_Stop_DMA()
2567 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_IC_Stop_DMA()
2574 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_IC_Stop_DMA()
2575 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_IC_Stop_DMA()
2582 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_IC_Stop_DMA()
2583 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_IC_Stop_DMA()
2595 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop_DMA()
2598 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_DMA()
2599 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_DMA()
2647 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) in HAL_TIM_OnePulse_Init() argument
2650 if (htim == NULL) in HAL_TIM_OnePulse_Init()
2656 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_Init()
2657 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_OnePulse_Init()
2658 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_OnePulse_Init()
2660 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_OnePulse_Init()
2661 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_OnePulse_Init()
2663 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_OnePulse_Init()
2666 htim->Lock = HAL_UNLOCKED; in HAL_TIM_OnePulse_Init()
2670 TIM_ResetCallback(htim); in HAL_TIM_OnePulse_Init()
2672 if (htim->OnePulse_MspInitCallback == NULL) in HAL_TIM_OnePulse_Init()
2674 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_OnePulse_Init()
2677 htim->OnePulse_MspInitCallback(htim); in HAL_TIM_OnePulse_Init()
2680 HAL_TIM_OnePulse_MspInit(htim); in HAL_TIM_OnePulse_Init()
2685 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_Init()
2688 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_OnePulse_Init()
2691 htim->Instance->CR1 &= ~TIM_CR1_OPM; in HAL_TIM_OnePulse_Init()
2694 htim->Instance->CR1 |= OnePulseMode; in HAL_TIM_OnePulse_Init()
2697 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_OnePulse_Init()
2700 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2701 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2702 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2703 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2706 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OnePulse_Init()
2716 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_DeInit() argument
2719 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_DeInit()
2721 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_DeInit()
2724 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_DeInit()
2727 if (htim->OnePulse_MspDeInitCallback == NULL) in HAL_TIM_OnePulse_DeInit()
2729 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_OnePulse_DeInit()
2732 htim->OnePulse_MspDeInitCallback(htim); in HAL_TIM_OnePulse_DeInit()
2735 HAL_TIM_OnePulse_MspDeInit(htim); in HAL_TIM_OnePulse_DeInit()
2739 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_OnePulse_DeInit()
2742 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2743 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2744 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2745 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2748 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_OnePulse_DeInit()
2751 __HAL_UNLOCK(htim); in HAL_TIM_OnePulse_DeInit()
2761 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_MspInit() argument
2764 UNUSED(htim); in HAL_TIM_OnePulse_MspInit()
2776 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_MspDeInit() argument
2779 UNUSED(htim); in HAL_TIM_OnePulse_MspDeInit()
2796 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Start() argument
2798 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_OnePulse_Start()
2799 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_OnePulse_Start()
2800 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start()
2801 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start()
2816 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2817 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2818 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2819 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2830 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start()
2831 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start()
2833 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Start()
2836 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OnePulse_Start()
2853 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Stop() argument
2864 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop()
2865 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop()
2867 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Stop()
2870 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OnePulse_Stop()
2874 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_Stop()
2877 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2878 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2879 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2880 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2896 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Start_IT() argument
2898 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_OnePulse_Start_IT()
2899 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_OnePulse_Start_IT()
2900 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start_IT()
2901 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start_IT()
2916 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2917 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2918 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2919 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2931 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OnePulse_Start_IT()
2934 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OnePulse_Start_IT()
2936 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start_IT()
2937 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start_IT()
2939 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Start_IT()
2942 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OnePulse_Start_IT()
2959 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Stop_IT() argument
2965 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OnePulse_Stop_IT()
2968 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OnePulse_Stop_IT()
2975 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop_IT()
2976 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop_IT()
2978 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Stop_IT()
2981 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OnePulse_Stop_IT()
2985 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_Stop_IT()
2988 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
2989 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
2990 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
2991 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
3038 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sCon… in HAL_TIM_Encoder_Init() argument
3045 if (htim == NULL) in HAL_TIM_Encoder_Init()
3051 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Init()
3052 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_Encoder_Init()
3053 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_Encoder_Init()
3054 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_Encoder_Init()
3064 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_Encoder_Init()
3066 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_Encoder_Init()
3069 htim->Lock = HAL_UNLOCKED; in HAL_TIM_Encoder_Init()
3073 TIM_ResetCallback(htim); in HAL_TIM_Encoder_Init()
3075 if (htim->Encoder_MspInitCallback == NULL) in HAL_TIM_Encoder_Init()
3077 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_Encoder_Init()
3080 htim->Encoder_MspInitCallback(htim); in HAL_TIM_Encoder_Init()
3083 HAL_TIM_Encoder_MspInit(htim); in HAL_TIM_Encoder_Init()
3088 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Encoder_Init()
3091 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); in HAL_TIM_Encoder_Init()
3094 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_Encoder_Init()
3097 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_Encoder_Init()
3100 tmpccmr1 = htim->Instance->CCMR1; in HAL_TIM_Encoder_Init()
3103 tmpccer = htim->Instance->CCER; in HAL_TIM_Encoder_Init()
3124 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_Encoder_Init()
3127 htim->Instance->CCMR1 = tmpccmr1; in HAL_TIM_Encoder_Init()
3130 htim->Instance->CCER = tmpccer; in HAL_TIM_Encoder_Init()
3133 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_Encoder_Init()
3136 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3137 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3138 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3139 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3142 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Encoder_Init()
3153 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_DeInit() argument
3156 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_DeInit()
3158 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Encoder_DeInit()
3161 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_DeInit()
3164 if (htim->Encoder_MspDeInitCallback == NULL) in HAL_TIM_Encoder_DeInit()
3166 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_Encoder_DeInit()
3169 htim->Encoder_MspDeInitCallback(htim); in HAL_TIM_Encoder_DeInit()
3172 HAL_TIM_Encoder_MspDeInit(htim); in HAL_TIM_Encoder_DeInit()
3176 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_Encoder_DeInit()
3179 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3180 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3181 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3182 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3185 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_Encoder_DeInit()
3188 __HAL_UNLOCK(htim); in HAL_TIM_Encoder_DeInit()
3198 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_MspInit() argument
3201 UNUSED(htim); in HAL_TIM_Encoder_MspInit()
3213 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_MspDeInit() argument
3216 UNUSED(htim); in HAL_TIM_Encoder_MspDeInit()
3233 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Start() argument
3235 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start()
3236 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start()
3237 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start()
3238 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start()
3241 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start()
3253 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3254 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3266 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3267 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3281 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3282 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3283 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3284 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3293 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3299 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3305 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3306 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3311 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start()
3327 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop() argument
3330 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop()
3338 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3344 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3350 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3351 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3357 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop()
3362 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3363 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3367 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3368 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3369 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3370 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3387 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Start_IT() argument
3389 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start_IT()
3390 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start_IT()
3391 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_IT()
3392 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_IT()
3395 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start_IT()
3407 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3408 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3420 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3421 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3435 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3436 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3437 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3438 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3448 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3449 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Start_IT()
3455 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3456 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Start_IT()
3462 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3463 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3464 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Start_IT()
3465 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Start_IT()
3471 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_IT()
3487 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop_IT() argument
3490 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop_IT()
3496 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3499 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Stop_IT()
3503 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3506 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Stop_IT()
3510 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3511 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3514 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Stop_IT()
3515 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Stop_IT()
3519 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop_IT()
3524 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3525 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3529 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3530 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3531 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3532 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3552 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pD… in HAL_TIM_Encoder_Start_DMA() argument
3555 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start_DMA()
3556 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start_DMA()
3557 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_DMA()
3558 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_DMA()
3561 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start_DMA()
3580 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3581 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3605 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3606 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3634 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3635 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3636 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3637 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3651 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3652 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3655 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3658 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, in HAL_TIM_Encoder_Start_DMA()
3665 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Start_DMA()
3668 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3671 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3679 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3680 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3683 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; in HAL_TIM_Encoder_Start_DMA()
3685 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, in HAL_TIM_Encoder_Start_DMA()
3692 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Start_DMA()
3695 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3698 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3706 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3707 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3710 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3713 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, in HAL_TIM_Encoder_Start_DMA()
3721 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3722 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3725 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3728 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, in HAL_TIM_Encoder_Start_DMA()
3736 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Start_DMA()
3738 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Start_DMA()
3741 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3742 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3745 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3765 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop_DMA() argument
3768 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop_DMA()
3774 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3777 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Stop_DMA()
3778 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_Encoder_Stop_DMA()
3782 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3785 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Stop_DMA()
3786 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_Encoder_Stop_DMA()
3790 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3791 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3794 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Stop_DMA()
3795 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Stop_DMA()
3796 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_Encoder_Stop_DMA()
3797 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_Encoder_Stop_DMA()
3801 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop_DMA()
3806 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3807 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3811 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3812 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3813 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3814 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3842 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) in HAL_TIM_IRQHandler() argument
3844 uint32_t itsource = htim->Instance->DIER; in HAL_TIM_IRQHandler()
3845 uint32_t itflag = htim->Instance->SR; in HAL_TIM_IRQHandler()
3853 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); in HAL_TIM_IRQHandler()
3854 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in HAL_TIM_IRQHandler()
3857 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) in HAL_TIM_IRQHandler()
3860 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3862 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3869 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3870 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3872 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3873 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3876 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3885 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); in HAL_TIM_IRQHandler()
3886 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in HAL_TIM_IRQHandler()
3888 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) in HAL_TIM_IRQHandler()
3891 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3893 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3900 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3901 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3903 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3904 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3907 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3915 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); in HAL_TIM_IRQHandler()
3916 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in HAL_TIM_IRQHandler()
3918 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) in HAL_TIM_IRQHandler()
3921 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3923 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3930 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3931 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3933 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3934 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3937 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3945 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); in HAL_TIM_IRQHandler()
3946 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in HAL_TIM_IRQHandler()
3948 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) in HAL_TIM_IRQHandler()
3951 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3953 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3960 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3961 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3963 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3964 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3967 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3975 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); in HAL_TIM_IRQHandler()
3977 htim->PeriodElapsedCallback(htim); in HAL_TIM_IRQHandler()
3979 HAL_TIM_PeriodElapsedCallback(htim); in HAL_TIM_IRQHandler()
3989 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); in HAL_TIM_IRQHandler()
3991 htim->BreakCallback(htim); in HAL_TIM_IRQHandler()
3993 HAL_TIMEx_BreakCallback(htim); in HAL_TIM_IRQHandler()
4002 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); in HAL_TIM_IRQHandler()
4004 htim->Break2Callback(htim); in HAL_TIM_IRQHandler()
4006 HAL_TIMEx_Break2Callback(htim); in HAL_TIM_IRQHandler()
4015 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); in HAL_TIM_IRQHandler()
4017 htim->TriggerCallback(htim); in HAL_TIM_IRQHandler()
4019 HAL_TIM_TriggerCallback(htim); in HAL_TIM_IRQHandler()
4028 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); in HAL_TIM_IRQHandler()
4030 htim->CommutationCallback(htim); in HAL_TIM_IRQHandler()
4032 HAL_TIMEx_CommutCallback(htim); in HAL_TIM_IRQHandler()
4076 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, in HAL_TIM_OC_ConfigChannel() argument
4088 __HAL_LOCK(htim); in HAL_TIM_OC_ConfigChannel()
4095 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4098 TIM_OC1_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4105 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4108 TIM_OC2_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4115 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4118 TIM_OC3_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4125 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4128 TIM_OC4_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4135 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4138 TIM_OC5_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4145 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4148 TIM_OC6_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4157 __HAL_UNLOCK(htim); in HAL_TIM_OC_ConfigChannel()
4175 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConf… in HAL_TIM_IC_ConfigChannel() argument
4180 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4187 __HAL_LOCK(htim); in HAL_TIM_IC_ConfigChannel()
4192 TIM_TI1_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4198 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; in HAL_TIM_IC_ConfigChannel()
4201 htim->Instance->CCMR1 |= sConfig->ICPrescaler; in HAL_TIM_IC_ConfigChannel()
4206 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4208 TIM_TI2_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4214 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; in HAL_TIM_IC_ConfigChannel()
4217 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); in HAL_TIM_IC_ConfigChannel()
4222 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4224 TIM_TI3_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4230 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; in HAL_TIM_IC_ConfigChannel()
4233 htim->Instance->CCMR2 |= sConfig->ICPrescaler; in HAL_TIM_IC_ConfigChannel()
4238 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4240 TIM_TI4_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4246 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; in HAL_TIM_IC_ConfigChannel()
4249 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); in HAL_TIM_IC_ConfigChannel()
4256 __HAL_UNLOCK(htim); in HAL_TIM_IC_ConfigChannel()
4276 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, in HAL_TIM_PWM_ConfigChannel() argument
4289 __HAL_LOCK(htim); in HAL_TIM_PWM_ConfigChannel()
4296 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4299 TIM_OC1_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4302 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; in HAL_TIM_PWM_ConfigChannel()
4305 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; in HAL_TIM_PWM_ConfigChannel()
4306 htim->Instance->CCMR1 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4313 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4316 TIM_OC2_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4319 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; in HAL_TIM_PWM_ConfigChannel()
4322 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; in HAL_TIM_PWM_ConfigChannel()
4323 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4330 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4333 TIM_OC3_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4336 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; in HAL_TIM_PWM_ConfigChannel()
4339 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; in HAL_TIM_PWM_ConfigChannel()
4340 htim->Instance->CCMR2 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4347 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4350 TIM_OC4_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4353 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; in HAL_TIM_PWM_ConfigChannel()
4356 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; in HAL_TIM_PWM_ConfigChannel()
4357 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4364 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4367 TIM_OC5_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4370 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; in HAL_TIM_PWM_ConfigChannel()
4373 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; in HAL_TIM_PWM_ConfigChannel()
4374 htim->Instance->CCMR3 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4381 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4384 TIM_OC6_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4387 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; in HAL_TIM_PWM_ConfigChannel()
4390 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; in HAL_TIM_PWM_ConfigChannel()
4391 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4400 __HAL_UNLOCK(htim); in HAL_TIM_PWM_ConfigChannel()
4424 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef… in HAL_TIM_OnePulse_ConfigChannel() argument
4437 __HAL_LOCK(htim); in HAL_TIM_OnePulse_ConfigChannel()
4439 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_ConfigChannel()
4453 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4455 TIM_OC1_SetConfig(htim->Instance, &temp1); in HAL_TIM_OnePulse_ConfigChannel()
4461 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4463 TIM_OC2_SetConfig(htim->Instance, &temp1); in HAL_TIM_OnePulse_ConfigChannel()
4478 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4480 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, in HAL_TIM_OnePulse_ConfigChannel()
4484 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; in HAL_TIM_OnePulse_ConfigChannel()
4487 htim->Instance->SMCR &= ~TIM_SMCR_TS; in HAL_TIM_OnePulse_ConfigChannel()
4488 htim->Instance->SMCR |= TIM_TS_TI1FP1; in HAL_TIM_OnePulse_ConfigChannel()
4491 htim->Instance->SMCR &= ~TIM_SMCR_SMS; in HAL_TIM_OnePulse_ConfigChannel()
4492 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; in HAL_TIM_OnePulse_ConfigChannel()
4498 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4500 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, in HAL_TIM_OnePulse_ConfigChannel()
4504 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; in HAL_TIM_OnePulse_ConfigChannel()
4507 htim->Instance->SMCR &= ~TIM_SMCR_TS; in HAL_TIM_OnePulse_ConfigChannel()
4508 htim->Instance->SMCR |= TIM_TS_TI2FP2; in HAL_TIM_OnePulse_ConfigChannel()
4511 htim->Instance->SMCR &= ~TIM_SMCR_SMS; in HAL_TIM_OnePulse_ConfigChannel()
4512 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; in HAL_TIM_OnePulse_ConfigChannel()
4522 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OnePulse_ConfigChannel()
4524 __HAL_UNLOCK(htim); in HAL_TIM_OnePulse_ConfigChannel()
4579 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, in HAL_TIM_DMABurst_WriteStart() argument
4585 …status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bu… in HAL_TIM_DMABurst_WriteStart()
4638 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddre… in HAL_TIM_DMABurst_MultiWriteStart() argument
4645 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurst_MultiWriteStart()
4651 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) in HAL_TIM_DMABurst_MultiWriteStart()
4655 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) in HAL_TIM_DMABurst_MultiWriteStart()
4663 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; in HAL_TIM_DMABurst_MultiWriteStart()
4676 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4677 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4680 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4683 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4684 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4694 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4695 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4698 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4701 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4702 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4712 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4713 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4716 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4719 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4720 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4730 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4731 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4734 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4737 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4738 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4748 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4749 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4752 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4755 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4756 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4766 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4767 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4770 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4773 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4774 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4784 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4785 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4788 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4791 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4792 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4807 htim->Instance->DCR = (BurstBaseAddress | BurstLength); in HAL_TIM_DMABurst_MultiWriteStart()
4809 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_MultiWriteStart()
4822 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) in HAL_TIM_DMABurst_WriteStop() argument
4834 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_DMABurst_WriteStop()
4839 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_DMABurst_WriteStop()
4844 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_DMABurst_WriteStop()
4849 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_DMABurst_WriteStop()
4854 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_DMABurst_WriteStop()
4859 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); in HAL_TIM_DMABurst_WriteStop()
4864 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); in HAL_TIM_DMABurst_WriteStop()
4875 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_WriteStop()
4878 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_DMABurst_WriteStop()
4930 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, in HAL_TIM_DMABurst_ReadStart() argument
4935 …status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bur… in HAL_TIM_DMABurst_ReadStart()
4988 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddres… in HAL_TIM_DMABurst_MultiReadStart() argument
4995 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurst_MultiReadStart()
5001 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) in HAL_TIM_DMABurst_MultiReadStart()
5005 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) in HAL_TIM_DMABurst_MultiReadStart()
5013 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; in HAL_TIM_DMABurst_MultiReadStart()
5025 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_DMABurst_MultiReadStart()
5026 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5029 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5032 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)Bur… in HAL_TIM_DMABurst_MultiReadStart()
5043 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5044 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5047 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5050 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5061 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5062 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5065 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5068 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5079 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5080 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5083 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5086 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5097 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5098 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5101 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5104 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5115 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; in HAL_TIM_DMABurst_MultiReadStart()
5116 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5119 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5122 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_… in HAL_TIM_DMABurst_MultiReadStart()
5133 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; in HAL_TIM_DMABurst_MultiReadStart()
5134 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5137 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5140 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)Bu… in HAL_TIM_DMABurst_MultiReadStart()
5156 htim->Instance->DCR = (BurstBaseAddress | BurstLength); in HAL_TIM_DMABurst_MultiReadStart()
5159 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_MultiReadStart()
5172 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) in HAL_TIM_DMABurst_ReadStop() argument
5184 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_DMABurst_ReadStop()
5189 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_DMABurst_ReadStop()
5194 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_DMABurst_ReadStop()
5199 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_DMABurst_ReadStop()
5204 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_DMABurst_ReadStop()
5209 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); in HAL_TIM_DMABurst_ReadStop()
5214 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); in HAL_TIM_DMABurst_ReadStop()
5225 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_ReadStop()
5228 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_DMABurst_ReadStop()
5256 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) in HAL_TIM_GenerateEvent() argument
5259 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_GenerateEvent()
5263 __HAL_LOCK(htim); in HAL_TIM_GenerateEvent()
5266 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_GenerateEvent()
5269 htim->Instance->EGR = EventSource; in HAL_TIM_GenerateEvent()
5272 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_GenerateEvent()
5274 __HAL_UNLOCK(htim); in HAL_TIM_GenerateEvent()
5295 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, in HAL_TIM_ConfigOCrefClear() argument
5302 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); in HAL_TIM_ConfigOCrefClear()
5306 __HAL_LOCK(htim); in HAL_TIM_ConfigOCrefClear()
5308 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_ConfigOCrefClear()
5315 …CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM… in HAL_TIM_ConfigOCrefClear()
5318 CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); in HAL_TIM_ConfigOCrefClear()
5327 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); in HAL_TIM_ConfigOCrefClear()
5330 MODIFY_REG(htim->Instance->OR1, TIMx_OR1_OCREF_CLR, sClearInputConfig->ClearInputSource); in HAL_TIM_ConfigOCrefClear()
5344 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigOCrefClear()
5345 __HAL_UNLOCK(htim); in HAL_TIM_ConfigOCrefClear()
5349 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigOCrefClear()
5355 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); in HAL_TIM_ConfigOCrefClear()
5358 CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); in HAL_TIM_ConfigOCrefClear()
5376 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); in HAL_TIM_ConfigOCrefClear()
5381 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); in HAL_TIM_ConfigOCrefClear()
5390 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); in HAL_TIM_ConfigOCrefClear()
5395 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); in HAL_TIM_ConfigOCrefClear()
5404 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); in HAL_TIM_ConfigOCrefClear()
5409 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); in HAL_TIM_ConfigOCrefClear()
5418 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); in HAL_TIM_ConfigOCrefClear()
5423 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); in HAL_TIM_ConfigOCrefClear()
5432 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); in HAL_TIM_ConfigOCrefClear()
5437 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); in HAL_TIM_ConfigOCrefClear()
5446 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); in HAL_TIM_ConfigOCrefClear()
5451 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); in HAL_TIM_ConfigOCrefClear()
5460 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigOCrefClear()
5462 __HAL_UNLOCK(htim); in HAL_TIM_ConfigOCrefClear()
5474 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *… in HAL_TIM_ConfigClockSource() argument
5480 __HAL_LOCK(htim); in HAL_TIM_ConfigClockSource()
5482 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_ConfigClockSource()
5488 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_ConfigClockSource()
5491 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_ConfigClockSource()
5497 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5504 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5512 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigClockSource()
5518 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_ConfigClockSource()
5521 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_ConfigClockSource()
5528 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5536 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigClockSource()
5541 htim->Instance->SMCR |= TIM_SMCR_ECE; in HAL_TIM_ConfigClockSource()
5548 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5554 TIM_TI1_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5557 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); in HAL_TIM_ConfigClockSource()
5564 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5570 TIM_TI2_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5573 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); in HAL_TIM_ConfigClockSource()
5580 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5586 TIM_TI1_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5589 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); in HAL_TIM_ConfigClockSource()
5599 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5601 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); in HAL_TIM_ConfigClockSource()
5609 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigClockSource()
5611 __HAL_UNLOCK(htim); in HAL_TIM_ConfigClockSource()
5628 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) in HAL_TIM_ConfigTI1Input() argument
5633 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); in HAL_TIM_ConfigTI1Input()
5637 tmpcr2 = htim->Instance->CR2; in HAL_TIM_ConfigTI1Input()
5646 htim->Instance->CR2 = tmpcr2; in HAL_TIM_ConfigTI1Input()
5660 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef … in HAL_TIM_SlaveConfigSynchro() argument
5663 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); in HAL_TIM_SlaveConfigSynchro()
5667 __HAL_LOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5669 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_SlaveConfigSynchro()
5671 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) in HAL_TIM_SlaveConfigSynchro()
5673 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro()
5674 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5679 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); in HAL_TIM_SlaveConfigSynchro()
5682 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); in HAL_TIM_SlaveConfigSynchro()
5684 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro()
5686 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5700 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, in HAL_TIM_SlaveConfigSynchro_IT() argument
5704 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); in HAL_TIM_SlaveConfigSynchro_IT()
5708 __HAL_LOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5710 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_SlaveConfigSynchro_IT()
5712 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) in HAL_TIM_SlaveConfigSynchro_IT()
5714 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro_IT()
5715 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5720 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); in HAL_TIM_SlaveConfigSynchro_IT()
5723 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); in HAL_TIM_SlaveConfigSynchro_IT()
5725 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro_IT()
5727 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5743 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_ReadCapturedValue() argument
5752 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5755 tmpreg = htim->Instance->CCR1; in HAL_TIM_ReadCapturedValue()
5762 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5765 tmpreg = htim->Instance->CCR2; in HAL_TIM_ReadCapturedValue()
5773 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5776 tmpreg = htim->Instance->CCR3; in HAL_TIM_ReadCapturedValue()
5784 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5787 tmpreg = htim->Instance->CCR4; in HAL_TIM_ReadCapturedValue()
5827 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PeriodElapsedCallback() argument
5830 UNUSED(htim); in HAL_TIM_PeriodElapsedCallback()
5842 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PeriodElapsedHalfCpltCallback() argument
5845 UNUSED(htim); in HAL_TIM_PeriodElapsedHalfCpltCallback()
5857 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_OC_DelayElapsedCallback() argument
5860 UNUSED(htim); in HAL_TIM_OC_DelayElapsedCallback()
5872 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) in HAL_TIM_IC_CaptureCallback() argument
5875 UNUSED(htim); in HAL_TIM_IC_CaptureCallback()
5887 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_IC_CaptureHalfCpltCallback() argument
5890 UNUSED(htim); in HAL_TIM_IC_CaptureHalfCpltCallback()
5902 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_PulseFinishedCallback() argument
5905 UNUSED(htim); in HAL_TIM_PWM_PulseFinishedCallback()
5917 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_PulseFinishedHalfCpltCallback() argument
5920 UNUSED(htim); in HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
5932 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) in HAL_TIM_TriggerCallback() argument
5935 UNUSED(htim); in HAL_TIM_TriggerCallback()
5947 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_TriggerHalfCpltCallback() argument
5950 UNUSED(htim); in HAL_TIM_TriggerHalfCpltCallback()
5962 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) in HAL_TIM_ErrorCallback() argument
5965 UNUSED(htim); in HAL_TIM_ErrorCallback()
6009 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Callb… in HAL_TIM_RegisterCallback() argument
6019 if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_RegisterCallback()
6024 htim->Base_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6028 htim->Base_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6032 htim->IC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6036 htim->IC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6040 htim->OC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6044 htim->OC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6048 htim->PWM_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6052 htim->PWM_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6056 htim->OnePulse_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6060 htim->OnePulse_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6064 htim->Encoder_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6068 htim->Encoder_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6072 htim->HallSensor_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6076 htim->HallSensor_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6080 htim->PeriodElapsedCallback = pCallback; in HAL_TIM_RegisterCallback()
6084 htim->PeriodElapsedHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6088 htim->TriggerCallback = pCallback; in HAL_TIM_RegisterCallback()
6092 htim->TriggerHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6096 htim->IC_CaptureCallback = pCallback; in HAL_TIM_RegisterCallback()
6100 htim->IC_CaptureHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6104 htim->OC_DelayElapsedCallback = pCallback; in HAL_TIM_RegisterCallback()
6108 htim->PWM_PulseFinishedCallback = pCallback; in HAL_TIM_RegisterCallback()
6112 htim->PWM_PulseFinishedHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6116 htim->ErrorCallback = pCallback; in HAL_TIM_RegisterCallback()
6120 htim->CommutationCallback = pCallback; in HAL_TIM_RegisterCallback()
6124 htim->CommutationHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6128 htim->BreakCallback = pCallback; in HAL_TIM_RegisterCallback()
6132 htim->Break2Callback = pCallback; in HAL_TIM_RegisterCallback()
6141 else if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_RegisterCallback()
6146 htim->Base_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6150 htim->Base_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6154 htim->IC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6158 htim->IC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6162 htim->OC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6166 htim->OC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6170 htim->PWM_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6174 htim->PWM_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6178 htim->OnePulse_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6182 htim->OnePulse_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6186 htim->Encoder_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6190 htim->Encoder_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6194 htim->HallSensor_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6198 htim->HallSensor_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6252 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Cal… in HAL_TIM_UnRegisterCallback() argument
6256 if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_UnRegisterCallback()
6262 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_UnRegisterCallback()
6267 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_UnRegisterCallback()
6272 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_UnRegisterCallback()
6277 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6282 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_UnRegisterCallback()
6287 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6292 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_UnRegisterCallback()
6297 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_UnRegisterCallback()
6302 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_UnRegisterCallback()
6307 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_UnRegisterCallback()
6312 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_UnRegisterCallback()
6317 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_UnRegisterCallback()
6322 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; in HAL_TIM_UnRegisterCallback()
6327 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; in HAL_TIM_UnRegisterCallback()
6332 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; in HAL_TIM_UnRegisterCallback()
6337 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6342 htim->TriggerCallback = HAL_TIM_TriggerCallback; in HAL_TIM_UnRegisterCallback()
6347 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6352 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; in HAL_TIM_UnRegisterCallback()
6357 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6362 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; in HAL_TIM_UnRegisterCallback()
6367 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; in HAL_TIM_UnRegisterCallback()
6372 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6377 htim->ErrorCallback = HAL_TIM_ErrorCallback; in HAL_TIM_UnRegisterCallback()
6382 htim->CommutationCallback = HAL_TIMEx_CommutCallback; in HAL_TIM_UnRegisterCallback()
6387 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6392 htim->BreakCallback = HAL_TIMEx_BreakCallback; in HAL_TIM_UnRegisterCallback()
6397 htim->Break2Callback = HAL_TIMEx_Break2Callback; in HAL_TIM_UnRegisterCallback()
6406 else if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_UnRegisterCallback()
6412 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_UnRegisterCallback()
6417 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_UnRegisterCallback()
6422 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_UnRegisterCallback()
6427 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6432 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_UnRegisterCallback()
6437 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6442 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_UnRegisterCallback()
6447 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_UnRegisterCallback()
6452 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_UnRegisterCallback()
6457 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_UnRegisterCallback()
6462 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_UnRegisterCallback()
6467 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_UnRegisterCallback()
6472 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; in HAL_TIM_UnRegisterCallback()
6477 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; in HAL_TIM_UnRegisterCallback()
6520 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_Base_GetState() argument
6522 return htim->State; in HAL_TIM_Base_GetState()
6530 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_OC_GetState() argument
6532 return htim->State; in HAL_TIM_OC_GetState()
6540 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_PWM_GetState() argument
6542 return htim->State; in HAL_TIM_PWM_GetState()
6550 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_IC_GetState() argument
6552 return htim->State; in HAL_TIM_IC_GetState()
6560 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_GetState() argument
6562 return htim->State; in HAL_TIM_OnePulse_GetState()
6570 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_GetState() argument
6572 return htim->State; in HAL_TIM_Encoder_GetState()
6580 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) in HAL_TIM_GetActiveChannel() argument
6582 return htim->Channel; in HAL_TIM_GetActiveChannel()
6598 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channe… in HAL_TIM_GetChannelState() argument
6603 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_GetChannelState()
6605 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_GetChannelState()
6615 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) in HAL_TIM_DMABurstState() argument
6618 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurstState()
6620 return htim->DMABurstState; in HAL_TIM_DMABurstState()
6642 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAError() local
6644 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMAError()
6646 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMAError()
6647 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6649 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMAError()
6651 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMAError()
6652 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6654 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMAError()
6656 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMAError()
6657 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6659 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMAError()
6661 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMAError()
6662 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6666 htim->State = HAL_TIM_STATE_READY; in TIM_DMAError()
6670 htim->ErrorCallback(htim); in TIM_DMAError()
6672 HAL_TIM_ErrorCallback(htim); in TIM_DMAError()
6675 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMAError()
6685 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMADelayPulseCplt() local
6687 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMADelayPulseCplt()
6689 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMADelayPulseCplt()
6693 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6696 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMADelayPulseCplt()
6698 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMADelayPulseCplt()
6702 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6705 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMADelayPulseCplt()
6707 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMADelayPulseCplt()
6711 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6714 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMADelayPulseCplt()
6716 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMADelayPulseCplt()
6720 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6729 htim->PWM_PulseFinishedCallback(htim); in TIM_DMADelayPulseCplt()
6731 HAL_TIM_PWM_PulseFinishedCallback(htim); in TIM_DMADelayPulseCplt()
6734 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMADelayPulseCplt()
6744 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMADelayPulseHalfCplt() local
6746 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMADelayPulseHalfCplt()
6748 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMADelayPulseHalfCplt()
6750 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMADelayPulseHalfCplt()
6752 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMADelayPulseHalfCplt()
6754 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMADelayPulseHalfCplt()
6756 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMADelayPulseHalfCplt()
6758 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMADelayPulseHalfCplt()
6760 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMADelayPulseHalfCplt()
6768 htim->PWM_PulseFinishedHalfCpltCallback(htim); in TIM_DMADelayPulseHalfCplt()
6770 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); in TIM_DMADelayPulseHalfCplt()
6773 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMADelayPulseHalfCplt()
6783 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMACaptureCplt() local
6785 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMACaptureCplt()
6787 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMACaptureCplt()
6791 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6792 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6795 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMACaptureCplt()
6797 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMACaptureCplt()
6801 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6802 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6805 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMACaptureCplt()
6807 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMACaptureCplt()
6811 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6812 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6815 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMACaptureCplt()
6817 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMACaptureCplt()
6821 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6822 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6831 htim->IC_CaptureCallback(htim); in TIM_DMACaptureCplt()
6833 HAL_TIM_IC_CaptureCallback(htim); in TIM_DMACaptureCplt()
6836 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMACaptureCplt()
6846 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMACaptureHalfCplt() local
6848 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMACaptureHalfCplt()
6850 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMACaptureHalfCplt()
6852 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMACaptureHalfCplt()
6854 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMACaptureHalfCplt()
6856 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMACaptureHalfCplt()
6858 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMACaptureHalfCplt()
6860 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMACaptureHalfCplt()
6862 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMACaptureHalfCplt()
6870 htim->IC_CaptureHalfCpltCallback(htim); in TIM_DMACaptureHalfCplt()
6872 HAL_TIM_IC_CaptureHalfCpltCallback(htim); in TIM_DMACaptureHalfCplt()
6875 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMACaptureHalfCplt()
6885 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAPeriodElapsedCplt() local
6887 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) in TIM_DMAPeriodElapsedCplt()
6889 htim->State = HAL_TIM_STATE_READY; in TIM_DMAPeriodElapsedCplt()
6893 htim->PeriodElapsedCallback(htim); in TIM_DMAPeriodElapsedCplt()
6895 HAL_TIM_PeriodElapsedCallback(htim); in TIM_DMAPeriodElapsedCplt()
6906 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAPeriodElapsedHalfCplt() local
6909 htim->PeriodElapsedHalfCpltCallback(htim); in TIM_DMAPeriodElapsedHalfCplt()
6911 HAL_TIM_PeriodElapsedHalfCpltCallback(htim); in TIM_DMAPeriodElapsedHalfCplt()
6922 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMATriggerCplt() local
6924 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) in TIM_DMATriggerCplt()
6926 htim->State = HAL_TIM_STATE_READY; in TIM_DMATriggerCplt()
6930 htim->TriggerCallback(htim); in TIM_DMATriggerCplt()
6932 HAL_TIM_TriggerCallback(htim); in TIM_DMATriggerCplt()
6943 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMATriggerHalfCplt() local
6946 htim->TriggerHalfCpltCallback(htim); in TIM_DMATriggerHalfCplt()
6948 HAL_TIM_TriggerHalfCpltCallback(htim); in TIM_DMATriggerHalfCplt()
7410 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, in TIM_SlaveTimer_SetConfig() argument
7419 tmpsmcr = htim->Instance->SMCR; in TIM_SlaveTimer_SetConfig()
7432 htim->Instance->SMCR = tmpsmcr; in TIM_SlaveTimer_SetConfig()
7440 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7445 TIM_ETR_SetConfig(htim->Instance, in TIM_SlaveTimer_SetConfig()
7455 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7464 tmpccer = htim->Instance->CCER; in TIM_SlaveTimer_SetConfig()
7465 htim->Instance->CCER &= ~TIM_CCER_CC1E; in TIM_SlaveTimer_SetConfig()
7466 tmpccmr1 = htim->Instance->CCMR1; in TIM_SlaveTimer_SetConfig()
7473 htim->Instance->CCMR1 = tmpccmr1; in TIM_SlaveTimer_SetConfig()
7474 htim->Instance->CCER = tmpccer; in TIM_SlaveTimer_SetConfig()
7481 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7486 TIM_TI1_ConfigInputStage(htim->Instance, in TIM_SlaveTimer_SetConfig()
7495 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7500 TIM_TI2_ConfigInputStage(htim->Instance, in TIM_SlaveTimer_SetConfig()
7512 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7894 void TIM_ResetCallback(TIM_HandleTypeDef *htim) in TIM_ResetCallback() argument
7897 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; in TIM_ResetCallback()
7898 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; in TIM_ResetCallback()
7899 htim->TriggerCallback = HAL_TIM_TriggerCallback; in TIM_ResetCallback()
7900 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; in TIM_ResetCallback()
7901 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; in TIM_ResetCallback()
7902 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; in TIM_ResetCallback()
7903 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; in TIM_ResetCallback()
7904 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; in TIM_ResetCallback()
7905 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; in TIM_ResetCallback()
7906 htim->ErrorCallback = HAL_TIM_ErrorCallback; in TIM_ResetCallback()
7907 htim->CommutationCallback = HAL_TIMEx_CommutCallback; in TIM_ResetCallback()
7908 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; in TIM_ResetCallback()
7909 htim->BreakCallback = HAL_TIMEx_BreakCallback; in TIM_ResetCallback()
7910 htim->Break2Callback = HAL_TIMEx_Break2Callback; in TIM_ResetCallback()