112 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32…
113 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
114 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
152 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)  in HAL_DMA_Init()  argument
155   if (hdma == NULL)  in HAL_DMA_Init()
161   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));  in HAL_DMA_Init()
162   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));  in HAL_DMA_Init()
163   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));  in HAL_DMA_Init()
164   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));  in HAL_DMA_Init()
165   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));  in HAL_DMA_Init()
166   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));  in HAL_DMA_Init()
167   assert_param(IS_DMA_MODE(hdma->Init.Mode));  in HAL_DMA_Init()
168   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));  in HAL_DMA_Init()
170   assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));  in HAL_DMA_Init()
174   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))  in HAL_DMA_Init()
177     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / \  in HAL_DMA_Init()
179     hdma->DmaBaseAddress = DMA1;  in HAL_DMA_Init()
184     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / \  in HAL_DMA_Init()
186     hdma->DmaBaseAddress = DMA2;  in HAL_DMA_Init()
189   hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / \  in HAL_DMA_Init()
194   hdma->State = HAL_DMA_STATE_BUSY;  in HAL_DMA_Init()
197   CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \  in HAL_DMA_Init()
202   SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction           |                               \  in HAL_DMA_Init()
203                                 hdma->Init.PeriphInc           | hdma->Init.MemInc           | \  in HAL_DMA_Init()
204                                 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | \  in HAL_DMA_Init()
205                                 hdma->Init.Mode                | hdma->Init.Priority));  in HAL_DMA_Init()
210   DMA_CalcDMAMUXChannelBaseAndMask(hdma);  in HAL_DMA_Init()
212   if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)  in HAL_DMA_Init()
215     hdma->Init.Request = DMA_REQUEST_MEM2MEM;  in HAL_DMA_Init()
219   hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);  in HAL_DMA_Init()
222   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;  in HAL_DMA_Init()
224   if (((hdma->Init.Request >  0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))  in HAL_DMA_Init()
229     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);  in HAL_DMA_Init()
232     hdma->DMAmuxRequestGen->RGCR = 0U;  in HAL_DMA_Init()
235     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;  in HAL_DMA_Init()
239     hdma->DMAmuxRequestGen = 0U;  in HAL_DMA_Init()
240     hdma->DMAmuxRequestGenStatus = 0U;  in HAL_DMA_Init()
241     hdma->DMAmuxRequestGenStatusMask = 0U;  in HAL_DMA_Init()
245   hdma->ErrorCode = HAL_DMA_ERROR_NONE;  in HAL_DMA_Init()
248   hdma->State = HAL_DMA_STATE_READY;  in HAL_DMA_Init()
251   __HAL_UNLOCK(hdma);  in HAL_DMA_Init()
262 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)  in HAL_DMA_DeInit()  argument
265   if (NULL == hdma)  in HAL_DMA_DeInit()
271   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));  in HAL_DMA_DeInit()
274   __HAL_DMA_DISABLE(hdma);  in HAL_DMA_DeInit()
278   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))  in HAL_DMA_DeInit()
281     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / \  in HAL_DMA_DeInit()
283     hdma->DmaBaseAddress = DMA1;  in HAL_DMA_DeInit()
288     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / \  in HAL_DMA_DeInit()
290     hdma->DmaBaseAddress = DMA2;  in HAL_DMA_DeInit()
293   hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / \  in HAL_DMA_DeInit()
298   hdma->Instance->CCR = 0U;  in HAL_DMA_DeInit()
302   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));  in HAL_DMA_DeInit()
304   __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));  in HAL_DMA_DeInit()
310   DMA_CalcDMAMUXChannelBaseAndMask(hdma);  in HAL_DMA_DeInit()
313   hdma->DMAmuxChannel->CCR = 0U;  in HAL_DMA_DeInit()
316   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;  in HAL_DMA_DeInit()
319   if (((hdma->Init.Request >  0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))  in HAL_DMA_DeInit()
324     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);  in HAL_DMA_DeInit()
327     hdma->DMAmuxRequestGen->RGCR = 0U;  in HAL_DMA_DeInit()
330     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;  in HAL_DMA_DeInit()
333   hdma->DMAmuxRequestGen = 0U;  in HAL_DMA_DeInit()
334   hdma->DMAmuxRequestGenStatus = 0U;  in HAL_DMA_DeInit()
335   hdma->DMAmuxRequestGenStatusMask = 0U;  in HAL_DMA_DeInit()
338   hdma->XferCpltCallback = NULL;  in HAL_DMA_DeInit()
339   hdma->XferHalfCpltCallback = NULL;  in HAL_DMA_DeInit()
340   hdma->XferErrorCallback = NULL;  in HAL_DMA_DeInit()
341   hdma->XferAbortCallback = NULL;  in HAL_DMA_DeInit()
344   hdma->ErrorCode = HAL_DMA_ERROR_NONE;  in HAL_DMA_DeInit()
347   hdma->State = HAL_DMA_STATE_RESET;  in HAL_DMA_DeInit()
350   __HAL_UNLOCK(hdma);  in HAL_DMA_DeInit()
388 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, …  in HAL_DMA_Start()  argument
396   __HAL_LOCK(hdma);  in HAL_DMA_Start()
398   if (hdma->State == HAL_DMA_STATE_READY)  in HAL_DMA_Start()
401     hdma->State = HAL_DMA_STATE_BUSY;  in HAL_DMA_Start()
404     hdma->ErrorCode = HAL_DMA_ERROR_NONE;  in HAL_DMA_Start()
407     __HAL_DMA_DISABLE(hdma);  in HAL_DMA_Start()
410     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);  in HAL_DMA_Start()
413     __HAL_DMA_ENABLE(hdma);  in HAL_DMA_Start()
418     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;  in HAL_DMA_Start()
421     __HAL_UNLOCK(hdma);  in HAL_DMA_Start()
439 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres…  in HAL_DMA_Start_IT()  argument
448   __HAL_LOCK(hdma);  in HAL_DMA_Start_IT()
450   if (hdma->State == HAL_DMA_STATE_READY)  in HAL_DMA_Start_IT()
453     hdma->State = HAL_DMA_STATE_BUSY;  in HAL_DMA_Start_IT()
454     hdma->ErrorCode = HAL_DMA_ERROR_NONE;  in HAL_DMA_Start_IT()
457     __HAL_DMA_DISABLE(hdma);  in HAL_DMA_Start_IT()
460     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);  in HAL_DMA_Start_IT()
464     if (NULL != hdma->XferHalfCpltCallback)  in HAL_DMA_Start_IT()
467       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));  in HAL_DMA_Start_IT()
471       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);  in HAL_DMA_Start_IT()
472       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));  in HAL_DMA_Start_IT()
476     if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)  in HAL_DMA_Start_IT()
479       hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;  in HAL_DMA_Start_IT()
482     if (hdma->DMAmuxRequestGen != 0U)  in HAL_DMA_Start_IT()
486       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;  in HAL_DMA_Start_IT()
490     __HAL_DMA_ENABLE(hdma);  in HAL_DMA_Start_IT()
495     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;  in HAL_DMA_Start_IT()
498     __HAL_UNLOCK(hdma);  in HAL_DMA_Start_IT()
513 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)  in HAL_DMA_Abort()  argument
516   if (NULL == hdma)  in HAL_DMA_Abort()
522   if (hdma->State != HAL_DMA_STATE_BUSY)  in HAL_DMA_Abort()
524     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;  in HAL_DMA_Abort()
527     __HAL_UNLOCK(hdma);  in HAL_DMA_Abort()
534     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));  in HAL_DMA_Abort()
537     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;  in HAL_DMA_Abort()
540     __HAL_DMA_DISABLE(hdma);  in HAL_DMA_Abort()
544     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));  in HAL_DMA_Abort()
546     __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex  & 0x1CU)));  in HAL_DMA_Abort()
550     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;  in HAL_DMA_Abort()
552     if (hdma->DMAmuxRequestGen != 0U)  in HAL_DMA_Abort()
556       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;  in HAL_DMA_Abort()
559       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;  in HAL_DMA_Abort()
563     hdma->State = HAL_DMA_STATE_READY;  in HAL_DMA_Abort()
566     __HAL_UNLOCK(hdma);  in HAL_DMA_Abort()
578 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)  in HAL_DMA_Abort_IT()  argument
582   if (hdma->State != HAL_DMA_STATE_BUSY)  in HAL_DMA_Abort_IT()
585     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;  in HAL_DMA_Abort_IT()
592     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));  in HAL_DMA_Abort_IT()
595     __HAL_DMA_DISABLE(hdma);  in HAL_DMA_Abort_IT()
598     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;  in HAL_DMA_Abort_IT()
602     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));  in HAL_DMA_Abort_IT()
604     __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));  in HAL_DMA_Abort_IT()
608     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;  in HAL_DMA_Abort_IT()
610     if (hdma->DMAmuxRequestGen != 0U)  in HAL_DMA_Abort_IT()
614       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;  in HAL_DMA_Abort_IT()
617       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;  in HAL_DMA_Abort_IT()
621     hdma->State = HAL_DMA_STATE_READY;  in HAL_DMA_Abort_IT()
624     __HAL_UNLOCK(hdma);  in HAL_DMA_Abort_IT()
627     if (hdma->XferAbortCallback != NULL)  in HAL_DMA_Abort_IT()
629       hdma->XferAbortCallback(hdma);  in HAL_DMA_Abort_IT()
643 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com…  argument
649   if (hdma->State != HAL_DMA_STATE_BUSY)
652     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
653     __HAL_UNLOCK(hdma);
658   if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
660     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
668     temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);
673     temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);
680   while ((hdma->DmaBaseAddress->ISR & temp) == 0U)
682     if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U)
687       hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
690       hdma->ErrorCode = HAL_DMA_ERROR_TE;
693       hdma->State = HAL_DMA_STATE_READY;
696       __HAL_UNLOCK(hdma);
701   while (0U == __HAL_DMA_GET_FLAG(hdma, temp))
703     if (0U != __HAL_DMA_GET_FLAG(hdma, (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))))
708       __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
711       hdma->ErrorCode = HAL_DMA_ERROR_TE;
714       hdma->State = HAL_DMA_STATE_READY;
717       __HAL_UNLOCK(hdma);
728         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
731         hdma->State = HAL_DMA_STATE_READY;
734         __HAL_UNLOCK(hdma);
742   if (hdma->DMAmuxRequestGen != 0U)
745     if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
748       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
751       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
754       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
759   if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
762     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
765     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
772     hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU));
774     __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
778     __HAL_UNLOCK(hdma);
782     hdma->State = HAL_DMA_STATE_READY;
788     hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
790     __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
803 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)  argument
806   uint32_t flag_it = hdma->DmaBaseAddress->ISR;
810   uint32_t source_it = hdma->Instance->CCR;
813 …if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT)…
816     if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
819       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
823     hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
825     __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
831     if (hdma->XferHalfCpltCallback != NULL)
834       hdma->XferHalfCpltCallback(hdma);
839 …else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it &…
841     if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
844       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
846       hdma->State = HAL_DMA_STATE_READY;
849     __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
851     __HAL_UNLOCK(hdma);
852     if (hdma->XferCpltCallback != NULL)
855       hdma->XferCpltCallback(hdma);
860 …else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_I…
865     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
869     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
871     __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
875     hdma->ErrorCode = HAL_DMA_ERROR_TE;
878     hdma->State = HAL_DMA_STATE_READY;
881     __HAL_UNLOCK(hdma);
883     if (hdma->XferErrorCallback != NULL)
886       hdma->XferErrorCallback(hdma);
906 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb…  argument
912   __HAL_LOCK(hdma);
914   if (hdma->State == HAL_DMA_STATE_READY)
919         hdma->XferCpltCallback = pCallback;
923         hdma->XferHalfCpltCallback = pCallback;
927         hdma->XferErrorCallback = pCallback;
931         hdma->XferAbortCallback = pCallback;
945   __HAL_UNLOCK(hdma);
958 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal…  argument
963   __HAL_LOCK(hdma);
965   if (hdma->State == HAL_DMA_STATE_READY)
970         hdma->XferCpltCallback = NULL;
974         hdma->XferHalfCpltCallback = NULL;
978         hdma->XferErrorCallback = NULL;
982         hdma->XferAbortCallback = NULL;
986         hdma->XferCpltCallback = NULL;
987         hdma->XferHalfCpltCallback = NULL;
988         hdma->XferErrorCallback = NULL;
989         hdma->XferAbortCallback = NULL;
1003   __HAL_UNLOCK(hdma);
1034 HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma)  argument
1037   return hdma->State;
1046 uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma)  argument
1049   return hdma->ErrorCode;
1073 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32…  argument
1076   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
1078   if (hdma->DMAmuxRequestGen != 0U)
1081     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
1086   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
1088   __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
1092   hdma->Instance->CNDTR = DataLength;
1095   if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
1098     hdma->Instance->CPAR = DstAddress;
1101     hdma->Instance->CMAR = SrcAddress;
1107     hdma->Instance->CPAR = SrcAddress;
1110     hdma->Instance->CMAR = DstAddress;
1120 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)  argument
1126   if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
1130     hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
1133     channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
1139     hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));
1142     channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U);
1146   hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *) \
1148                                    ((hdma->ChannelIndex >> 2U) * \
1152   channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
1156   hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
1160   hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
1170 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)  argument
1172   uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
1175 …hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenera…
1178   hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
1181   hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);