Lines Matching refs:PWR
34 #if defined(PWR)
189 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
190 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
191 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
192 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
194 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
196 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
243 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
250 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
281 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); in LL_PWR_SetPowerMode()
296 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); in LL_PWR_GetPowerMode()
306 SET_BIT(PWR->CR1, PWR_CR1_FPD_STOP); in LL_PWR_EnableFlashPWRDownModeDuringStop()
316 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_STOP); in LL_PWR_DisableFlashPWRDownModeDuringStop()
326 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_STOP) == (PWR_CR1_FPD_STOP)) ? 1UL : 0UL); in LL_PWR_IsEnabledFlashPWRDownModeDuringSTOP()
336 SET_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN); in LL_PWR_EnableFlashPWRDownModeDuringLPRun()
346 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN); in LL_PWR_DisableFlashPWRDownModeDuringLPRun()
356 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN) == (PWR_CR1_FPD_LPRUN)) ? 1UL : 0UL); in LL_PWR_IsEnabledFlashPWRDownModeDuringLPRun()
366 SET_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP); in LL_PWR_EnableFlashPWRDownModeDuringSleeep()
376 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP); in LL_PWR_DisableFlashPWRDownModeDuringSleeep()
386 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP) == (PWR_CR1_FPD_LPSLP)) ? 1UL : 0UL); in LL_PWR_IsEnabledFlashPWRDownModeDuringSleeep()
396 SET_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_EnableBkUpAccess()
406 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_DisableBkUpAccess()
416 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpAccess()
429 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
441 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); in LL_PWR_GetRegulVoltageScaling()
450 SET_BIT(PWR->CR1, PWR_CR1_LPR); in LL_PWR_EnableLowPowerRunMode()
460 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); in LL_PWR_DisableLowPowerRunMode()
489 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL); in LL_PWR_IsEnabledLowPowerRunMode()
499 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
509 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
519 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
538 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); in LL_PWR_SetPVDLevel()
556 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); in LL_PWR_GetPVDLevel()
574 SET_BIT(PWR->CR2, PeriphVoltage); in LL_PWR_EnablePVM()
592 CLEAR_BIT(PWR->CR2, PeriphVoltage); in LL_PWR_DisablePVM()
610 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVM()
621 SET_BIT(PWR->CR2, PWR_CR2_USV); in LL_PWR_EnableVddUSB()
631 CLEAR_BIT(PWR->CR2, PWR_CR2_USV); in LL_PWR_DisableVddUSB()
641 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddUSB()
664 SET_BIT(PWR->CR3, WakeUpPin); in LL_PWR_EnableWakeUpPin()
686 CLEAR_BIT(PWR->CR3, WakeUpPin); in LL_PWR_DisableWakeUpPin()
708 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
718 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, LL_PWR_FULL_SRAM_RETENTION); in LL_PWR_EnableSRAMRetention()
728 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_DisableSRAMRetention()
738 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (LL_PWR_FULL_SRAM_RETENTION)) ? 1UL : 0UL); in LL_PWR_IsEnabledSRAMRetention()
753 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAMSize); in LL_PWR_SetSRAMContentRetention()
765 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS)); in LL_PWR_GetSRAMContentRetention()
775 SET_BIT(PWR->CR3, PWR_CR3_ENULP); in LL_PWR_EnableBORPVD_ULP()
785 CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP); in LL_PWR_DisableBORPVD_ULP()
795 return ((READ_BIT(PWR->CR3, PWR_CR3_ENULP) == (PWR_CR3_ENULP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBORPVD_ULP()
805 SET_BIT(PWR->CR3, PWR_CR3_APC); in LL_PWR_EnablePUPDCfg()
815 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); in LL_PWR_DisablePUPDCfg()
825 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); in LL_PWR_IsEnabledPUPDCfg()
835 SET_BIT(PWR->CR3, PWR_CR3_EIWUL); in LL_PWR_EnableInternWU()
845 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); in LL_PWR_DisableInternWU()
855 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL); in LL_PWR_IsEnabledInternWU()
877 SET_BIT(PWR->CR4, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityLow()
899 CLEAR_BIT(PWR->CR4, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityHigh()
921 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsWakeUpPinPolarityLow()
931 SET_BIT(PWR->CR4, PWR_CR4_VBE); in LL_PWR_EnableBatteryCharging()
941 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); in LL_PWR_DisableBatteryCharging()
951 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL); in LL_PWR_IsEnabledBatteryCharging()
964 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
976 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); in LL_PWR_GetBattChargResistor()
1227 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
1237 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
1247 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
1257 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU4()
1267 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU5()
1277 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF7) == (PWR_SR1_WUF7)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU7()
1287 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SB()
1297 return ((READ_BIT(PWR->SR1, LL_PWR_SR1_STOP0) == (LL_PWR_SR1_STOP0)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_Stop0()
1307 return ((READ_BIT(PWR->SR1, LL_PWR_SR1_STOP1) == (LL_PWR_SR1_STOP1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_Stop1()
1316 return ((READ_BIT(PWR->SR1, LL_PWR_SR1_STOP2) == (LL_PWR_SR1_STOP2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_Stop2()
1326 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_InternWU()
1336 return ((READ_BIT(PWR->SR2, PWR_SR2_FLASH_RDY) == (PWR_SR2_FLASH_RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_FLASH_RDY()
1346 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPS()
1358 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPF()
1369 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
1379 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
1390 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVMO_1()
1401 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVMO_3()
1411 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVMO_4()
1421 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); in LL_PWR_ClearFlag_WU1()
1431 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); in LL_PWR_ClearFlag_WU2()
1441 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); in LL_PWR_ClearFlag_WU3()
1451 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); in LL_PWR_ClearFlag_WU4()
1461 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); in LL_PWR_ClearFlag_WU5()
1471 WRITE_REG(PWR->SCR, PWR_SCR_CWUF7); in LL_PWR_ClearFlag_WU7()
1481 WRITE_REG(PWR->SCR, PWR_SCR_CSBF); in LL_PWR_ClearFlag_CSB()