276   uint32_t pllcfgr, pllsource, pllbypass, ic_divider;  in SystemCoreClockUpdate()  local
306       pllcfgr = READ_REG(RCC->PLL1CFGR1);  in SystemCoreClockUpdate()
307       pllsource = pllcfgr & RCC_PLL1CFGR1_PLL1SEL;  in SystemCoreClockUpdate()
308       pllbypass = pllcfgr & RCC_PLL1CFGR1_PLL1BYP;  in SystemCoreClockUpdate()
311         pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >>  RCC_PLL1CFGR1_PLL1DIVM_Pos;  in SystemCoreClockUpdate()
312         plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >>  RCC_PLL1CFGR1_PLL1DIVN_Pos;  in SystemCoreClockUpdate()
314         pllcfgr = READ_REG(RCC->PLL1CFGR3);  in SystemCoreClockUpdate()
315         pllp1 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV1) >>  RCC_PLL1CFGR3_PLL1PDIV1_Pos;  in SystemCoreClockUpdate()
316         pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >>  RCC_PLL1CFGR3_PLL1PDIV2_Pos;  in SystemCoreClockUpdate()
320       pllcfgr = READ_REG(RCC->PLL2CFGR1);  in SystemCoreClockUpdate()
321       pllsource = pllcfgr & RCC_PLL2CFGR1_PLL2SEL;  in SystemCoreClockUpdate()
322       pllbypass = pllcfgr & RCC_PLL2CFGR1_PLL2BYP;  in SystemCoreClockUpdate()
325         pllm = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVM) >>  RCC_PLL2CFGR1_PLL2DIVM_Pos;  in SystemCoreClockUpdate()
326         plln = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVN) >>  RCC_PLL2CFGR1_PLL2DIVN_Pos;  in SystemCoreClockUpdate()
328         pllcfgr = READ_REG(RCC->PLL2CFGR3);  in SystemCoreClockUpdate()
329         pllp1 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV1) >>  RCC_PLL2CFGR3_PLL2PDIV1_Pos;  in SystemCoreClockUpdate()
330         pllp2 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV2) >>  RCC_PLL2CFGR3_PLL2PDIV2_Pos;  in SystemCoreClockUpdate()
335       pllcfgr = READ_REG(RCC->PLL3CFGR1);  in SystemCoreClockUpdate()
336       pllsource = pllcfgr & RCC_PLL3CFGR1_PLL3SEL;  in SystemCoreClockUpdate()
337       pllbypass = pllcfgr & RCC_PLL3CFGR1_PLL3BYP;  in SystemCoreClockUpdate()
340         pllm = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVM) >>  RCC_PLL3CFGR1_PLL3DIVM_Pos;  in SystemCoreClockUpdate()
341         plln = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVN) >>  RCC_PLL3CFGR1_PLL3DIVN_Pos;  in SystemCoreClockUpdate()
343         pllcfgr = READ_REG(RCC->PLL3CFGR3);  in SystemCoreClockUpdate()
344         pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >>  RCC_PLL3CFGR3_PLL3PDIV1_Pos;  in SystemCoreClockUpdate()
345         pllp2 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV2) >>  RCC_PLL3CFGR3_PLL3PDIV2_Pos;  in SystemCoreClockUpdate()
350       pllcfgr = READ_REG(RCC->PLL4CFGR1);  in SystemCoreClockUpdate()
351       pllsource = pllcfgr & RCC_PLL4CFGR1_PLL4SEL;  in SystemCoreClockUpdate()
352       pllbypass = pllcfgr & RCC_PLL4CFGR1_PLL4BYP;  in SystemCoreClockUpdate()
355         pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >>  RCC_PLL4CFGR1_PLL4DIVM_Pos;  in SystemCoreClockUpdate()
356         plln = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVN) >>  RCC_PLL4CFGR1_PLL4DIVN_Pos;  in SystemCoreClockUpdate()
358         pllcfgr = READ_REG(RCC->PLL4CFGR3);  in SystemCoreClockUpdate()
359         pllp1 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV1) >>  RCC_PLL4CFGR3_PLL4PDIV1_Pos;  in SystemCoreClockUpdate()
360         pllp2 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV2) >>  RCC_PLL4CFGR3_PLL4PDIV2_Pos;  in SystemCoreClockUpdate()