333   uint32_t pllcfgr, pllsource, pllbypass, ic_divider;  in SystemCoreClockUpdate()  local
363       pllcfgr = READ_REG(RCC->PLL1CFGR1);  in SystemCoreClockUpdate()
364       pllsource = pllcfgr & RCC_PLL1CFGR1_PLL1SEL;  in SystemCoreClockUpdate()
365       pllbypass = pllcfgr & RCC_PLL1CFGR1_PLL1BYP;  in SystemCoreClockUpdate()
368         pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >>  RCC_PLL1CFGR1_PLL1DIVM_Pos;  in SystemCoreClockUpdate()
369         plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >>  RCC_PLL1CFGR1_PLL1DIVN_Pos;  in SystemCoreClockUpdate()
371         pllcfgr = READ_REG(RCC->PLL1CFGR3);  in SystemCoreClockUpdate()
372         pllp1 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV1) >>  RCC_PLL1CFGR3_PLL1PDIV1_Pos;  in SystemCoreClockUpdate()
373         pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >>  RCC_PLL1CFGR3_PLL1PDIV2_Pos;  in SystemCoreClockUpdate()
377       pllcfgr = READ_REG(RCC->PLL2CFGR1);  in SystemCoreClockUpdate()
378       pllsource = pllcfgr & RCC_PLL2CFGR1_PLL2SEL;  in SystemCoreClockUpdate()
379       pllbypass = pllcfgr & RCC_PLL2CFGR1_PLL2BYP;  in SystemCoreClockUpdate()
382         pllm = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVM) >>  RCC_PLL2CFGR1_PLL2DIVM_Pos;  in SystemCoreClockUpdate()
383         plln = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVN) >>  RCC_PLL2CFGR1_PLL2DIVN_Pos;  in SystemCoreClockUpdate()
385         pllcfgr = READ_REG(RCC->PLL2CFGR3);  in SystemCoreClockUpdate()
386         pllp1 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV1) >>  RCC_PLL2CFGR3_PLL2PDIV1_Pos;  in SystemCoreClockUpdate()
387         pllp2 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV2) >>  RCC_PLL2CFGR3_PLL2PDIV2_Pos;  in SystemCoreClockUpdate()
392       pllcfgr = READ_REG(RCC->PLL3CFGR1);  in SystemCoreClockUpdate()
393       pllsource = pllcfgr & RCC_PLL3CFGR1_PLL3SEL;  in SystemCoreClockUpdate()
394       pllbypass = pllcfgr & RCC_PLL3CFGR1_PLL3BYP;  in SystemCoreClockUpdate()
397         pllm = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVM) >>  RCC_PLL3CFGR1_PLL3DIVM_Pos;  in SystemCoreClockUpdate()
398         plln = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVN) >>  RCC_PLL3CFGR1_PLL3DIVN_Pos;  in SystemCoreClockUpdate()
400         pllcfgr = READ_REG(RCC->PLL3CFGR3);  in SystemCoreClockUpdate()
401         pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >>  RCC_PLL3CFGR3_PLL3PDIV1_Pos;  in SystemCoreClockUpdate()
402         pllp2 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV2) >>  RCC_PLL3CFGR3_PLL3PDIV2_Pos;  in SystemCoreClockUpdate()
407       pllcfgr = READ_REG(RCC->PLL4CFGR1);  in SystemCoreClockUpdate()
408       pllsource = pllcfgr & RCC_PLL4CFGR1_PLL4SEL;  in SystemCoreClockUpdate()
409       pllbypass = pllcfgr & RCC_PLL4CFGR1_PLL4BYP;  in SystemCoreClockUpdate()
412         pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >>  RCC_PLL4CFGR1_PLL4DIVM_Pos;  in SystemCoreClockUpdate()
413         plln = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVN) >>  RCC_PLL4CFGR1_PLL4DIVN_Pos;  in SystemCoreClockUpdate()
415         pllcfgr = READ_REG(RCC->PLL4CFGR3);  in SystemCoreClockUpdate()
416         pllp1 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV1) >>  RCC_PLL4CFGR3_PLL4PDIV1_Pos;  in SystemCoreClockUpdate()
417         pllp2 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV2) >>  RCC_PLL4CFGR3_PLL4PDIV2_Pos;  in SystemCoreClockUpdate()