Lines Matching refs:hcacheaxi
138 static HAL_StatusTypeDef CACHEAXI_CommandByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t Command,
177 HAL_StatusTypeDef HAL_CACHEAXI_Init(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Init() argument
182 if (hcacheaxi == NULL) in HAL_CACHEAXI_Init()
188 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Init()
190 if (hcacheaxi->State == HAL_CACHEAXI_STATE_RESET) in HAL_CACHEAXI_Init()
194 hcacheaxi->ErrorCallback = HAL_CACHEAXI_ErrorCallback; in HAL_CACHEAXI_Init()
195 hcacheaxi->CleanByAddrCallback = HAL_CACHEAXI_CleanByAddrCallback; in HAL_CACHEAXI_Init()
196 hcacheaxi->InvalidateCompleteCallback = HAL_CACHEAXI_InvalidateCompleteCallback; in HAL_CACHEAXI_Init()
197 hcacheaxi->CleanAndInvalidateByAddrCallback = HAL_CACHEAXI_CleanAndInvalidateByAddrCallback; in HAL_CACHEAXI_Init()
199 if (hcacheaxi->MspInitCallback == NULL) in HAL_CACHEAXI_Init()
201 hcacheaxi->MspInitCallback = HAL_CACHEAXI_MspInit; in HAL_CACHEAXI_Init()
205 hcacheaxi->MspInitCallback(hcacheaxi); in HAL_CACHEAXI_Init()
208 HAL_CACHEAXI_MspInit(hcacheaxi); in HAL_CACHEAXI_Init()
213 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE; in HAL_CACHEAXI_Init()
216 hcacheaxi->State = HAL_CACHEAXI_STATE_READY; in HAL_CACHEAXI_Init()
219 status = HAL_CACHEAXI_Enable(hcacheaxi); in HAL_CACHEAXI_Init()
230 HAL_StatusTypeDef HAL_CACHEAXI_DeInit(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_DeInit() argument
235 if (hcacheaxi == NULL) in HAL_CACHEAXI_DeInit()
241 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_DeInit()
244 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE; in HAL_CACHEAXI_DeInit()
247 hcacheaxi->State = HAL_CACHEAXI_STATE_RESET; in HAL_CACHEAXI_DeInit()
250 status = HAL_CACHEAXI_Disable(hcacheaxi); in HAL_CACHEAXI_DeInit()
253 (void)HAL_CACHEAXI_Monitor_Reset(hcacheaxi, CACHEAXI_MONITOR_ALL); in HAL_CACHEAXI_DeInit()
256 WRITE_REG(hcacheaxi->Instance->CR1, 0U); in HAL_CACHEAXI_DeInit()
257 WRITE_REG(hcacheaxi->Instance->CR2, 0U); in HAL_CACHEAXI_DeInit()
258 WRITE_REG(hcacheaxi->Instance->CMDRSADDRR, 0U); in HAL_CACHEAXI_DeInit()
259 WRITE_REG(hcacheaxi->Instance->CMDREADDRR, 0U); in HAL_CACHEAXI_DeInit()
260 WRITE_REG(hcacheaxi->Instance->FCR, 0U); in HAL_CACHEAXI_DeInit()
261 WRITE_REG(hcacheaxi->Instance->IER, 0U); in HAL_CACHEAXI_DeInit()
264 if (hcacheaxi->MspDeInitCallback == NULL) in HAL_CACHEAXI_DeInit()
266 hcacheaxi->MspDeInitCallback = HAL_CACHEAXI_MspDeInit; in HAL_CACHEAXI_DeInit()
270 hcacheaxi->MspDeInitCallback(hcacheaxi); in HAL_CACHEAXI_DeInit()
273 HAL_CACHEAXI_MspDeInit(hcacheaxi); in HAL_CACHEAXI_DeInit()
285 __weak void HAL_CACHEAXI_MspInit(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_MspInit() argument
288 UNUSED(hcacheaxi); in HAL_CACHEAXI_MspInit()
301 __weak void HAL_CACHEAXI_MspDeInit(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_MspDeInit() argument
304 UNUSED(hcacheaxi); in HAL_CACHEAXI_MspDeInit()
350 HAL_StatusTypeDef HAL_CACHEAXI_Enable(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Enable() argument
356 if (hcacheaxi == NULL) in HAL_CACHEAXI_Enable()
362 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Enable()
365 if (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_BUSYF) != 0U) in HAL_CACHEAXI_Enable()
370 while (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_BUSYF) != 0U) in HAL_CACHEAXI_Enable()
375 if (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_BUSYF) == 0U) in HAL_CACHEAXI_Enable()
378 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_TIMEOUT; in HAL_CACHEAXI_Enable()
390 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE; in HAL_CACHEAXI_Enable()
392 SET_BIT(hcacheaxi->Instance->CR1, CACHEAXI_CR1_EN); in HAL_CACHEAXI_Enable()
404 HAL_StatusTypeDef HAL_CACHEAXI_Disable(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Disable() argument
411 if (hcacheaxi == NULL) in HAL_CACHEAXI_Disable()
417 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Disable()
420 if (HAL_CACHEAXI_IsEnabled(hcacheaxi) != 0U) in HAL_CACHEAXI_Disable()
423 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE; in HAL_CACHEAXI_Disable()
426 hcacheaxi->State = HAL_CACHEAXI_STATE_READY; in HAL_CACHEAXI_Disable()
429 CLEAR_BIT(hcacheaxi->Instance->CR1, CACHEAXI_CR1_EN); in HAL_CACHEAXI_Disable()
435 while (READ_BIT(hcacheaxi->Instance->SR, (CACHEAXI_SR_BUSYF | CACHEAXI_SR_BUSYCMDF)) != 0U) in HAL_CACHEAXI_Disable()
439 if (READ_BIT(hcacheaxi->Instance->SR, (CACHEAXI_SR_BUSYF | CACHEAXI_SR_BUSYCMDF)) != 0U) in HAL_CACHEAXI_Disable()
442 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_TIMEOUT; in HAL_CACHEAXI_Disable()
445 hcacheaxi->State = HAL_CACHEAXI_STATE_READY; in HAL_CACHEAXI_Disable()
463 uint32_t HAL_CACHEAXI_IsEnabled(const CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_IsEnabled() argument
465 return ((READ_BIT(hcacheaxi->Instance->CR1, CACHEAXI_CR1_EN) != 0U) ? 1UL : 0UL); in HAL_CACHEAXI_IsEnabled()
475 HAL_StatusTypeDef HAL_CACHEAXI_Invalidate(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Invalidate() argument
481 if (hcacheaxi == NULL) in HAL_CACHEAXI_Invalidate()
487 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Invalidate()
490 if (READ_BIT(hcacheaxi->Instance->SR, (CACHEAXI_SR_BUSYF | CACHEAXI_SR_BUSYCMDF)) != 0U) in HAL_CACHEAXI_Invalidate()
498 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE; in HAL_CACHEAXI_Invalidate()
501 hcacheaxi->State = HAL_CACHEAXI_STATE_READY; in HAL_CACHEAXI_Invalidate()
504 WRITE_REG(hcacheaxi->Instance->FCR, (CACHEAXI_FCR_CBSYENDF | CACHEAXI_FCR_CCMDENDF)); in HAL_CACHEAXI_Invalidate()
507 MODIFY_REG(hcacheaxi->Instance->CR2, CACHEAXI_CR2_CACHECMD, 0U); in HAL_CACHEAXI_Invalidate()
510 SET_BIT(hcacheaxi->Instance->CR1, CACHEAXI_CR1_CACHEINV); in HAL_CACHEAXI_Invalidate()
516 while (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_BUSYF) != 0U) in HAL_CACHEAXI_Invalidate()
520 if (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_BUSYF) != 0U) in HAL_CACHEAXI_Invalidate()
523 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_TIMEOUT; in HAL_CACHEAXI_Invalidate()
526 hcacheaxi->State = HAL_CACHEAXI_STATE_ERROR; in HAL_CACHEAXI_Invalidate()
548 HAL_StatusTypeDef HAL_CACHEAXI_CleanByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const… in HAL_CACHEAXI_CleanByAddr() argument
554 if (hcacheaxi == NULL) in HAL_CACHEAXI_CleanByAddr()
560 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_CleanByAddr()
563 …status = CACHEAXI_CommandByAddr(hcacheaxi, CACHEAXI_COMMAND_CLEAN, pAddr, dSize, CACHEAXI_POLLING_… in HAL_CACHEAXI_CleanByAddr()
577 HAL_StatusTypeDef HAL_CACHEAXI_CleanInvalidByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t… in HAL_CACHEAXI_CleanInvalidByAddr() argument
583 if (hcacheaxi == NULL) in HAL_CACHEAXI_CleanInvalidByAddr()
589 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_CleanInvalidByAddr()
592 …status = CACHEAXI_CommandByAddr(hcacheaxi, CACHEAXI_COMMAND_CLEAN_INVALIDATE, pAddr, dSize, CACHEA… in HAL_CACHEAXI_CleanInvalidByAddr()
606 HAL_StatusTypeDef HAL_CACHEAXI_Invalidate_IT(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Invalidate_IT() argument
611 if (hcacheaxi == NULL) in HAL_CACHEAXI_Invalidate_IT()
617 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Invalidate_IT()
620 if (READ_BIT(hcacheaxi->Instance->SR, (CACHEAXI_SR_BUSYF | CACHEAXI_SR_BUSYCMDF)) != 0U) in HAL_CACHEAXI_Invalidate_IT()
628 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE; in HAL_CACHEAXI_Invalidate_IT()
631 hcacheaxi->State = HAL_CACHEAXI_STATE_READY; in HAL_CACHEAXI_Invalidate_IT()
634 WRITE_REG(hcacheaxi->Instance->FCR, (CACHEAXI_FCR_CBSYENDF | CACHEAXI_FCR_CCMDENDF)); in HAL_CACHEAXI_Invalidate_IT()
637 MODIFY_REG(hcacheaxi->Instance->CR2, CACHEAXI_CR2_CACHECMD, 0U); in HAL_CACHEAXI_Invalidate_IT()
640 SET_BIT(hcacheaxi->Instance->IER, CACHEAXI_IER_BSYENDIE); in HAL_CACHEAXI_Invalidate_IT()
643 SET_BIT(hcacheaxi->Instance->CR1, CACHEAXI_CR1_CACHEINV); in HAL_CACHEAXI_Invalidate_IT()
660 HAL_StatusTypeDef HAL_CACHEAXI_CleanByAddr_IT(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *co… in HAL_CACHEAXI_CleanByAddr_IT() argument
666 if (hcacheaxi == NULL) in HAL_CACHEAXI_CleanByAddr_IT()
672 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_CleanByAddr_IT()
675 …status = CACHEAXI_CommandByAddr(hcacheaxi, CACHEAXI_COMMAND_CLEAN, pAddr, dSize, CACHEAXI_IT_MODE); in HAL_CACHEAXI_CleanByAddr_IT()
691 HAL_StatusTypeDef HAL_CACHEAXI_CleanInvalidByAddr_IT(CACHEAXI_HandleTypeDef *hcacheaxi, const uint3… in HAL_CACHEAXI_CleanInvalidByAddr_IT() argument
697 if (hcacheaxi == NULL) in HAL_CACHEAXI_CleanInvalidByAddr_IT()
703 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_CleanInvalidByAddr_IT()
706 …status = CACHEAXI_CommandByAddr(hcacheaxi, CACHEAXI_COMMAND_CLEAN_INVALIDATE, pAddr, dSize, CACHEA… in HAL_CACHEAXI_CleanInvalidByAddr_IT()
728 HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Start(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorTyp… in HAL_CACHEAXI_Monitor_Start() argument
731 if (hcacheaxi == NULL) in HAL_CACHEAXI_Monitor_Start()
737 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Monitor_Start()
740 SET_BIT(hcacheaxi->Instance->CR1, MonitorType); in HAL_CACHEAXI_Monitor_Start()
763 HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Stop(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType) in HAL_CACHEAXI_Monitor_Stop() argument
766 if (hcacheaxi == NULL) in HAL_CACHEAXI_Monitor_Stop()
772 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Monitor_Stop()
775 CLEAR_BIT(hcacheaxi->Instance->CR1, MonitorType); in HAL_CACHEAXI_Monitor_Stop()
797 HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Reset(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorTyp… in HAL_CACHEAXI_Monitor_Reset() argument
800 if (hcacheaxi == NULL) in HAL_CACHEAXI_Monitor_Reset()
806 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Monitor_Reset()
810 SET_BIT(hcacheaxi->Instance->CR1, (MonitorType << 2U)); in HAL_CACHEAXI_Monitor_Reset()
811 CLEAR_BIT(hcacheaxi->Instance->CR1, (MonitorType << 2U)); in HAL_CACHEAXI_Monitor_Reset()
823 uint32_t HAL_CACHEAXI_Monitor_GetReadHitValue(const CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Monitor_GetReadHitValue() argument
826 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Monitor_GetReadHitValue()
829 return hcacheaxi->Instance->RHMONR; in HAL_CACHEAXI_Monitor_GetReadHitValue()
839 uint32_t HAL_CACHEAXI_Monitor_GetReadMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Monitor_GetReadMissValue() argument
842 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Monitor_GetReadMissValue()
845 return hcacheaxi->Instance->RMMONR; in HAL_CACHEAXI_Monitor_GetReadMissValue()
855 uint32_t HAL_CACHEAXI_Monitor_GetWriteHitValue(const CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Monitor_GetWriteHitValue() argument
858 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Monitor_GetWriteHitValue()
861 return hcacheaxi->Instance->WHMONR; in HAL_CACHEAXI_Monitor_GetWriteHitValue()
871 uint32_t HAL_CACHEAXI_Monitor_GetWriteMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Monitor_GetWriteMissValue() argument
874 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Monitor_GetWriteMissValue()
877 return hcacheaxi->Instance->WMMONR; in HAL_CACHEAXI_Monitor_GetWriteMissValue()
887 uint32_t HAL_CACHEAXI_Monitor_GetReadAllocMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Monitor_GetReadAllocMissValue() argument
890 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Monitor_GetReadAllocMissValue()
893 return hcacheaxi->Instance->RAMMONR; in HAL_CACHEAXI_Monitor_GetReadAllocMissValue()
903 uint32_t HAL_CACHEAXI_Monitor_GetWriteAllocMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Monitor_GetWriteAllocMissValue() argument
906 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Monitor_GetWriteAllocMissValue()
909 return hcacheaxi->Instance->WAMMONR; in HAL_CACHEAXI_Monitor_GetWriteAllocMissValue()
919 uint32_t HAL_CACHEAXI_Monitor_GetWriteThroughValue(const CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Monitor_GetWriteThroughValue() argument
922 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Monitor_GetWriteThroughValue()
925 return hcacheaxi->Instance->WTMONR; in HAL_CACHEAXI_Monitor_GetWriteThroughValue()
935 uint32_t HAL_CACHEAXI_Monitor_GetEvictionValue(const CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_Monitor_GetEvictionValue() argument
938 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_Monitor_GetEvictionValue()
941 return hcacheaxi->Instance->EVIMONR; in HAL_CACHEAXI_Monitor_GetEvictionValue()
951 void HAL_CACHEAXI_IRQHandler(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_IRQHandler() argument
957 assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance)); in HAL_CACHEAXI_IRQHandler()
960 itflags = READ_REG(hcacheaxi->Instance->SR); in HAL_CACHEAXI_IRQHandler()
961 itsources = READ_REG(hcacheaxi->Instance->IER); in HAL_CACHEAXI_IRQHandler()
967 __HAL_CACHEAXI_CLEAR_FLAG(hcacheaxi, CACHEAXI_FLAG_ERROR); in HAL_CACHEAXI_IRQHandler()
970 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_EVICTION_CLEAN; in HAL_CACHEAXI_IRQHandler()
974 hcacheaxi->ErrorCallback(hcacheaxi); in HAL_CACHEAXI_IRQHandler()
977 HAL_CACHEAXI_ErrorCallback(hcacheaxi); in HAL_CACHEAXI_IRQHandler()
981 if (READ_BIT(hcacheaxi->Instance->CR2, CACHEAXI_CR2_CACHECMD) == 0U) in HAL_CACHEAXI_IRQHandler()
984 __HAL_CACHEAXI_CLEAR_FLAG(hcacheaxi, CACHEAXI_FLAG_BUSYEND); in HAL_CACHEAXI_IRQHandler()
988 hcacheaxi->InvalidateCompleteCallback(hcacheaxi); in HAL_CACHEAXI_IRQHandler()
991 HAL_CACHEAXI_InvalidateCompleteCallback(hcacheaxi); in HAL_CACHEAXI_IRQHandler()
996 else if (READ_BIT(hcacheaxi->Instance->CR1, CACHEAXI_COMMAND_CLEAN_INVALIDATE) == \ in HAL_CACHEAXI_IRQHandler()
1000 __HAL_CACHEAXI_CLEAR_FLAG(hcacheaxi, CACHEAXI_FLAG_CMDEND); in HAL_CACHEAXI_IRQHandler()
1004 hcacheaxi->CleanAndInvalidateByAddrCallback(hcacheaxi); in HAL_CACHEAXI_IRQHandler()
1007 HAL_CACHEAXI_CleanAndInvalidateByAddrCallback(hcacheaxi); in HAL_CACHEAXI_IRQHandler()
1015 __HAL_CACHEAXI_CLEAR_FLAG(hcacheaxi, CACHEAXI_FLAG_CMDEND); in HAL_CACHEAXI_IRQHandler()
1019 hcacheaxi->CleanByAddrCallback(hcacheaxi); in HAL_CACHEAXI_IRQHandler()
1022 HAL_CACHEAXI_CleanByAddrCallback(hcacheaxi); in HAL_CACHEAXI_IRQHandler()
1045 HAL_StatusTypeDef HAL_CACHEAXI_RegisterCallback(CACHEAXI_HandleTypeDef *hcacheaxi, in HAL_CACHEAXI_RegisterCallback() argument
1052 if (hcacheaxi == NULL) in HAL_CACHEAXI_RegisterCallback()
1060 hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK; in HAL_CACHEAXI_RegisterCallback()
1066 if (hcacheaxi->State == HAL_CACHEAXI_STATE_READY) in HAL_CACHEAXI_RegisterCallback()
1071 hcacheaxi->CleanByAddrCallback = pCallback; in HAL_CACHEAXI_RegisterCallback()
1075 hcacheaxi->CleanAndInvalidateByAddrCallback = pCallback; in HAL_CACHEAXI_RegisterCallback()
1079 hcacheaxi->InvalidateCompleteCallback = pCallback; in HAL_CACHEAXI_RegisterCallback()
1083 hcacheaxi->ErrorCallback = pCallback; in HAL_CACHEAXI_RegisterCallback()
1087 hcacheaxi->MspInitCallback = pCallback; in HAL_CACHEAXI_RegisterCallback()
1091 hcacheaxi->MspDeInitCallback = pCallback; in HAL_CACHEAXI_RegisterCallback()
1096 hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK; in HAL_CACHEAXI_RegisterCallback()
1103 else if (hcacheaxi->State == HAL_CACHEAXI_STATE_RESET) in HAL_CACHEAXI_RegisterCallback()
1108 hcacheaxi->MspInitCallback = pCallback; in HAL_CACHEAXI_RegisterCallback()
1112 hcacheaxi->MspDeInitCallback = pCallback; in HAL_CACHEAXI_RegisterCallback()
1117 hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK; in HAL_CACHEAXI_RegisterCallback()
1127 hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK; in HAL_CACHEAXI_RegisterCallback()
1151 HAL_StatusTypeDef HAL_CACHEAXI_UnRegisterCallback(CACHEAXI_HandleTypeDef *hcacheaxi, in HAL_CACHEAXI_UnRegisterCallback() argument
1157 if (hcacheaxi == NULL) in HAL_CACHEAXI_UnRegisterCallback()
1162 if (hcacheaxi->State == HAL_CACHEAXI_STATE_READY) in HAL_CACHEAXI_UnRegisterCallback()
1168 hcacheaxi->CleanByAddrCallback = HAL_CACHEAXI_CleanByAddrCallback; in HAL_CACHEAXI_UnRegisterCallback()
1173 hcacheaxi->CleanAndInvalidateByAddrCallback = HAL_CACHEAXI_CleanAndInvalidateByAddrCallback; in HAL_CACHEAXI_UnRegisterCallback()
1178 hcacheaxi->InvalidateCompleteCallback = HAL_CACHEAXI_InvalidateCompleteCallback; in HAL_CACHEAXI_UnRegisterCallback()
1183 hcacheaxi->ErrorCallback = HAL_CACHEAXI_ErrorCallback; in HAL_CACHEAXI_UnRegisterCallback()
1188 hcacheaxi->MspInitCallback = HAL_CACHEAXI_MspInit; in HAL_CACHEAXI_UnRegisterCallback()
1193 hcacheaxi->MspDeInitCallback = HAL_CACHEAXI_MspDeInit; in HAL_CACHEAXI_UnRegisterCallback()
1198 hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK; in HAL_CACHEAXI_UnRegisterCallback()
1205 else if (HAL_CACHEAXI_STATE_RESET == hcacheaxi->State) in HAL_CACHEAXI_UnRegisterCallback()
1211 hcacheaxi->MspInitCallback = HAL_CACHEAXI_MspInit; in HAL_CACHEAXI_UnRegisterCallback()
1216 hcacheaxi->MspDeInitCallback = HAL_CACHEAXI_MspDeInit; in HAL_CACHEAXI_UnRegisterCallback()
1221 hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK; in HAL_CACHEAXI_UnRegisterCallback()
1231 hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK; in HAL_CACHEAXI_UnRegisterCallback()
1248 __weak void HAL_CACHEAXI_CleanByAddrCallback(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_CleanByAddrCallback() argument
1251 UNUSED(hcacheaxi); in HAL_CACHEAXI_CleanByAddrCallback()
1264 __weak void HAL_CACHEAXI_CleanAndInvalidateByAddrCallback(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_CleanAndInvalidateByAddrCallback() argument
1267 UNUSED(hcacheaxi); in HAL_CACHEAXI_CleanAndInvalidateByAddrCallback()
1280 __weak void HAL_CACHEAXI_InvalidateCompleteCallback(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_InvalidateCompleteCallback() argument
1283 UNUSED(hcacheaxi); in HAL_CACHEAXI_InvalidateCompleteCallback()
1296 __weak void HAL_CACHEAXI_ErrorCallback(CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_ErrorCallback() argument
1299 UNUSED(hcacheaxi); in HAL_CACHEAXI_ErrorCallback()
1330 HAL_CACHEAXI_StateTypeDef HAL_CACHEAXI_GetState(const CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_GetState() argument
1333 return hcacheaxi->State; in HAL_CACHEAXI_GetState()
1342 uint32_t HAL_CACHEAXI_GetError(const CACHEAXI_HandleTypeDef *hcacheaxi) in HAL_CACHEAXI_GetError() argument
1345 return hcacheaxi->ErrorCode; in HAL_CACHEAXI_GetError()
1370 static HAL_StatusTypeDef CACHEAXI_CommandByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t Command, in CACHEAXI_CommandByAddr() argument
1378 if (READ_BIT(hcacheaxi->Instance->SR, (CACHEAXI_SR_BUSYF | CACHEAXI_SR_BUSYCMDF)) != 0U) in CACHEAXI_CommandByAddr()
1386 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE; in CACHEAXI_CommandByAddr()
1389 hcacheaxi->State = HAL_CACHEAXI_STATE_READY; in CACHEAXI_CommandByAddr()
1392 WRITE_REG(hcacheaxi->Instance->FCR, (CACHEAXI_FCR_CBSYENDF | CACHEAXI_FCR_CCMDENDF)); in CACHEAXI_CommandByAddr()
1395 WRITE_REG(hcacheaxi->Instance->CMDRSADDRR, op_addr); in CACHEAXI_CommandByAddr()
1398 WRITE_REG(hcacheaxi->Instance->CMDREADDRR, (op_addr + dSize - 1U)); in CACHEAXI_CommandByAddr()
1401 MODIFY_REG(hcacheaxi->Instance->CR2, CACHEAXI_CR2_CACHECMD, Command); in CACHEAXI_CommandByAddr()
1407 SET_BIT(hcacheaxi->Instance->IER, CACHEAXI_IER_CMDENDIE); in CACHEAXI_CommandByAddr()
1410 SET_BIT(hcacheaxi->Instance->CR2, CACHEAXI_CR2_STARTCMD); in CACHEAXI_CommandByAddr()
1415 CLEAR_BIT(hcacheaxi->Instance->IER, CACHEAXI_IER_CMDENDIE); in CACHEAXI_CommandByAddr()
1418 SET_BIT(hcacheaxi->Instance->CR2, CACHEAXI_CR2_STARTCMD); in CACHEAXI_CommandByAddr()
1424 while (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_CMDENDF) == 0U) in CACHEAXI_CommandByAddr()
1428 if (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_CMDENDF) == 0U) in CACHEAXI_CommandByAddr()
1431 hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_TIMEOUT; in CACHEAXI_CommandByAddr()
1434 hcacheaxi->State = HAL_CACHEAXI_STATE_ERROR; in CACHEAXI_CommandByAddr()