Lines Matching refs:DIVENSR
6361 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC1ENS); in LL_RCC_IC1_Enable()
6441 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC2ENS); in LL_RCC_IC2_Enable()
6521 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC3ENS); in LL_RCC_IC3_Enable()
6601 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC4ENS); in LL_RCC_IC4_Enable()
6681 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC5ENS); in LL_RCC_IC5_Enable()
6761 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC6ENS); in LL_RCC_IC6_Enable()
6841 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC7ENS); in LL_RCC_IC7_Enable()
6921 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC8ENS); in LL_RCC_IC8_Enable()
7001 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC9ENS); in LL_RCC_IC9_Enable()
7081 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC10ENS); in LL_RCC_IC10_Enable()
7161 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC11ENS); in LL_RCC_IC11_Enable()
7241 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC12ENS); in LL_RCC_IC12_Enable()
7321 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC13ENS); in LL_RCC_IC13_Enable()
7401 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC14ENS); in LL_RCC_IC14_Enable()
7481 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC15ENS); in LL_RCC_IC15_Enable()
7561 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC16ENS); in LL_RCC_IC16_Enable()
7641 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC17ENS); in LL_RCC_IC17_Enable()
7721 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC18ENS); in LL_RCC_IC18_Enable()
7801 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC19ENS); in LL_RCC_IC19_Enable()
7881 WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC20ENS); in LL_RCC_IC20_Enable()