Lines Matching refs:PWR
34 #if defined (PWR)
233 MODIFY_REG(PWR->CR1, PWR_CR1_SDEN, SupplySource); in LL_PWR_ConfigSupply()
246 return READ_BIT(PWR->CR1, PWR_CR1_SDEN); in LL_PWR_GetSupply()
258 SET_BIT(PWR->CR1, PWR_CR1_LPDS08V); in LL_PWR_EnableSMPSLPMode()
268 CLEAR_BIT(PWR->CR1, PWR_CR1_LPDS08V); in LL_PWR_DisableSMPSLPMode()
278 return ((READ_BIT(PWR->CR1, PWR_CR1_LPDS08V) == (PWR_CR1_LPDS08V)) ? 1UL : 0UL); in LL_PWR_IsEnabledSMPSLPMode()
288 SET_BIT(PWR->CR1, PWR_CR1_MODE_PDN); in LL_PWR_EnablePullDown()
298 CLEAR_BIT(PWR->CR1, PWR_CR1_MODE_PDN); in LL_PWR_DisablePullDown()
308 return ((READ_BIT(PWR->CR1, PWR_CR1_MODE_PDN) == (PWR_CR1_MODE_PDN)) ? 1UL : 0UL); in LL_PWR_IsEnabledPullDown()
319 MODIFY_REG(PWR->CR1, PWR_CR1_POPL, (PulseTime << PWR_CR1_POPL_Pos)); in LL_PWR_SetPwrONPulseLowTime()
329 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_POPL) >> PWR_CR1_POPL_Pos); in LL_PWR_GetPwrONPulseLowTime()
339 SET_BIT(PWR->CR2, PWR_CR2_PVDEN); in LL_PWR_EnablePVD()
349 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDEN); in LL_PWR_DisablePVD()
359 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDEN) == (PWR_CR2_PVDEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
369 SET_BIT(PWR->CR3, PWR_CR3_VCOREMONEN); in LL_PWR_EnableVCOREMonitoring()
379 CLEAR_BIT(PWR->CR3, PWR_CR3_VCOREMONEN); in LL_PWR_DisableVCOREMonitoring()
389 return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREMONEN) == (PWR_CR3_VCOREMONEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVCOREMonitoring()
402 MODIFY_REG(PWR->CR3, PWR_CR3_VCORELLS, Lowlevel); in LL_PWR_SetVCORELowLevelDetection()
414 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VCORELLS)); in LL_PWR_GetVCORELowLevelDetection()
429 SET_BIT(PWR->CR4, PWR_CR4_TCMRBSEN); in LL_PWR_EnableTCMSBRetention()
439 CLEAR_BIT(PWR->CR4, PWR_CR4_TCMRBSEN); in LL_PWR_DisableTCMSBRetention()
449 return ((READ_BIT(PWR->CR4, PWR_CR4_TCMRBSEN) == (PWR_CR4_TCMRBSEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledTCMSBRetention()
464 SET_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN); in LL_PWR_EnableTCMFLXSBRetention()
474 CLEAR_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN); in LL_PWR_DisableTCMFLXSBRetention()
484 return ((READ_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN) == (PWR_CR4_TCMFLXRBSEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledTCMFLXSBRetention()
497 MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
510 return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_ACTVOS) == (PWR_VOSCR_ACTVOS)) ? 1UL : 0UL); in LL_PWR_GetRegulVoltageScaling()
520 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in LL_PWR_EnableMonitoring()
530 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in LL_PWR_DisableMonitoring()
540 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledMonitoring()
554 SET_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN); in LL_PWR_EnableBkpSRAMSBRetention()
564 CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN); in LL_PWR_DisableBkpSRAMSBRetention()
574 return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN) == (PWR_BDCR2_BKPRBSEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkpSRAMSBRetention()
584 SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP); in LL_PWR_EnableBkUpAccess()
594 CLEAR_BIT(PWR->DBPCR, PWR_DBPCR_DBP); in LL_PWR_DisableBkUpAccess()
604 return ((READ_BIT(PWR->DBPCR, PWR_DBPCR_DBP) == (PWR_DBPCR_DBP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpAccess()
617 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_SVOS, VoltageScaling); in LL_PWR_SetStopModeRegulVoltageScaling()
629 return READ_BIT(PWR->CPUCR, PWR_CPUCR_SVOS); in LL_PWR_GetStopModeRegulVoltageScaling()
642 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS, PDMode); in LL_PWR_SetPowerDownModeDS()
654 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS)); in LL_PWR_GetPowerDownModeDS()
664 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV); in LL_PWR_EnableVddIO2()
674 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV); in LL_PWR_DisableVddIO2()
684 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV) == (PWR_SVMCR3_VDDIO2SV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO2()
694 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV); in LL_PWR_EnableVddIO3()
704 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV); in LL_PWR_DisableVddIO3()
714 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV) == (PWR_SVMCR3_VDDIO3SV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO3()
724 SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV); in LL_PWR_EnableVddIO4()
734 CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV); in LL_PWR_DisableVddIO4()
744 return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV) == (PWR_SVMCR1_VDDIO4SV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO4()
754 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV); in LL_PWR_EnableVddIO5()
764 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV); in LL_PWR_DisableVddIO5()
774 return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV) == (PWR_SVMCR2_VDDIO5SV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO5()
784 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV); in LL_PWR_EnableVddUSB()
794 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV); in LL_PWR_DisableVddUSB()
804 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV) == (PWR_SVMCR3_USB33SV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddUSB()
814 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV); in LL_PWR_EnableVddADC()
824 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV); in LL_PWR_DisableVddADC()
834 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV) == (PWR_SVMCR3_ASV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddADC()
844 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN); in LL_PWR_EnableVddIO2Monitoring()
854 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN); in LL_PWR_DisableVddIO2Monitoring()
864 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN) == (PWR_SVMCR3_VDDIO2VMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO2Monitoring()
874 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN); in LL_PWR_EnableVddIO3Monitoring()
884 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN); in LL_PWR_DisableVddIO3Monitoring()
894 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN) == (PWR_SVMCR3_VDDIO3VMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO3Monitoring()
904 SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN); in LL_PWR_EnableVddIO4Monitoring()
914 CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN); in LL_PWR_DisableVddIO4Monitoring()
924 return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN) == (PWR_SVMCR1_VDDIO4VMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO4Monitoring()
934 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN); in LL_PWR_EnableVddIO5Monitoring()
944 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN); in LL_PWR_DisableVddIO5Monitoring()
954 return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN) == (PWR_SVMCR2_VDDIO5VMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO5Monitoring()
964 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN); in LL_PWR_EnableVddADCMonitoring()
974 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN); in LL_PWR_DisableVddADCMonitoring()
984 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN) == (PWR_SVMCR3_AVMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddADCMonitoring()
994 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN); in LL_PWR_EnableVddUSBMonitoring()
1004 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN); in LL_PWR_DisableVddUSBMonitoring()
1014 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN) == (PWR_SVMCR3_USB33VMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddUSBMonitoring()
1030 MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL, (VoltageRange << PWR_SVMCR3_VDDIOVRSEL_Pos)); in LL_PWR_SetVddIOVoltageRange()
1042 return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL) >> PWR_SVMCR3_VDDIOVRSEL_Pos); in LL_PWR_GetVddIOVoltageRange()
1058 MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL, (VoltageRange << PWR_SVMCR3_VDDIO2VRSEL_Pos)); in LL_PWR_SetVddIO2VoltageRange()
1070 return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL) >> PWR_SVMCR3_VDDIO2VRSEL_Pos); in LL_PWR_GetVddIO2VoltageRange()
1086 MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL, (VoltageRange << PWR_SVMCR3_VDDIO3VRSEL_Pos)); in LL_PWR_SetVddIO3VoltageRange()
1098 return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL) >> PWR_SVMCR3_VDDIO3VRSEL_Pos); in LL_PWR_GetVddIO3VoltageRange()
1114 MODIFY_REG(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL, (VoltageRange << PWR_SVMCR1_VDDIO4VRSEL_Pos)); in LL_PWR_SetVddIO4VoltageRange()
1126 return (uint32_t)(READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL) >> PWR_SVMCR1_VDDIO4VRSEL_Pos); in LL_PWR_GetVddIO4VoltageRange()
1142 MODIFY_REG(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL, (VoltageRange << PWR_SVMCR2_VDDIO5VRSEL_Pos)); in LL_PWR_SetVddIO5VoltageRange()
1154 return (uint32_t)(READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL) >> PWR_SVMCR2_VDDIO5VRSEL_Pos); in LL_PWR_GetVddIO5VoltageRange()
1164 SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY); in LL_PWR_EnableVddIO4VoltageRangeSB()
1174 CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY); in LL_PWR_DisableVddIO4VoltageRangeSB()
1184 …return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY) == (PWR_SVMCR1_VDDIO4VRSTBY)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO4VoltageRangeSB()
1194 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY); in LL_PWR_EnableVddIO5VoltageRangeSB()
1204 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY); in LL_PWR_DisableVddIO5VoltageRangeSB()
1214 …return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY) == (PWR_SVMCR2_VDDIO5VRSTBY)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO5VoltageRangeSB()
1232 SET_BIT(PWR->WKUPEPR, WakeUpPin); in LL_PWR_EnableWakeUpPin()
1250 CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); in LL_PWR_DisableWakeUpPin()
1268 return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
1286 SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); in LL_PWR_SetWakeUpPinPolarityLow()
1304 CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); in LL_PWR_SetWakeUpPinPolarityHigh()
1322 …return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEP… in LL_PWR_IsWakeUpPinPolarityLow()
1340 MODIFY_REG(PWR->WKUPEPR, \ in LL_PWR_SetWakeUpPinPullNone()
1360 MODIFY_REG(PWR->WKUPEPR, \ in LL_PWR_SetWakeUpPinPullUp()
1380 MODIFY_REG(PWR->WKUPEPR, \ in LL_PWR_SetWakeUpPinPullDown()
1403 …uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHI… in LL_PWR_GetWakeUpPinPull()
1424 return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_ACTVOSRDY) == (PWR_VOSCR_ACTVOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_ACTVOSRDY()
1434 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDO) == (PWR_CR2_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
1444 return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREL) == (PWR_CR3_VCOREL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VCOREL()
1454 return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREH) == (PWR_CR3_VCOREH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VCOREH()
1465 return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_VOSRDY) == (PWR_VOSCR_VOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOSRDY()
1475 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_VBATL) == (PWR_BDCR1_VBATL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATL()
1485 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_VBATH) == (PWR_BDCR1_VBATH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATH()
1495 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_TEMPL) == (PWR_BDCR1_TEMPL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPL()
1505 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_TEMPH) == (PWR_BDCR1_TEMPH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPH()
1515 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_STOP()
1525 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SB()
1535 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2RDY) == (PWR_SVMCR3_VDDIO2RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VDDIO2RDY()
1545 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3RDY) == (PWR_SVMCR3_VDDIO3RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VDDIO3RDY()
1555 return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4RDY) == (PWR_SVMCR1_VDDIO4RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VDDIO4RDY()
1565 return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5RDY) == (PWR_SVMCR2_VDDIO5RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VDDIO5RDY()
1575 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_ARDY) == (PWR_SVMCR3_ARDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_ARDY()
1585 return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33RDY) == (PWR_SVMCR3_USB33RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_USB33RDY()
1595 return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF1) == (PWR_WKUPSR_WKUPF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
1605 return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF2) == (PWR_WKUPSR_WKUPF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
1615 return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF3) == (PWR_WKUPSR_WKUPF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
1625 return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF4) == (PWR_WKUPSR_WKUPF4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU4()
1635 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); in LL_PWR_ClearFlag_STOP_SB()
1645 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1); in LL_PWR_ClearFlag_WU1()
1655 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2); in LL_PWR_ClearFlag_WU2()
1665 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3); in LL_PWR_ClearFlag_WU3()
1675 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4); in LL_PWR_ClearFlag_WU4()
1685 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC); in LL_PWR_ClearFlag_WU()
1729 WRITE_REG(PWR->PRIVCFGR, PrivilegeConfig); in LL_PWR_ConfigPrivilege()
1762 return (READ_REG(PWR->PRIVCFGR)); in LL_PWR_GetConfigPrivilege()
1799 WRITE_REG(PWR->SECCFGR, SecureConfig); in LL_PWR_ConfigSecure()
1833 return (READ_REG(PWR->SECCFGR)); in LL_PWR_GetConfigSecure()