160 __STATIC_INLINE void LL_CACHEAXI_Enable(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_Enable()  argument
162   SET_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN);  in LL_CACHEAXI_Enable()
171 __STATIC_INLINE void LL_CACHEAXI_Disable(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_Disable()  argument
173   CLEAR_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN);  in LL_CACHEAXI_Disable()
182 __STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabled(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_IsEnabled()  argument
184   return ((READ_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN) == (CACHEAXI_CR1_EN)) ? 1UL : 0UL);  in LL_CACHEAXI_IsEnabled()
194 __STATIC_INLINE void LL_CACHEAXI_SetStartAddress(CACHEAXI_TypeDef *CACHEAXIx, uint32_t addr)  in LL_CACHEAXI_SetStartAddress()  argument
196   WRITE_REG(CACHEAXIx->CMDRSADDRR, addr);  in LL_CACHEAXI_SetStartAddress()
205 __STATIC_INLINE uint32_t LL_CACHEAXI_GetStartAddress(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_GetStartAddress()  argument
207   return (uint32_t)(READ_REG(CACHEAXIx->CMDRSADDRR));  in LL_CACHEAXI_GetStartAddress()
217 __STATIC_INLINE void LL_CACHEAXI_SetEndAddress(CACHEAXI_TypeDef *CACHEAXIx, uint32_t addr)  in LL_CACHEAXI_SetEndAddress()  argument
219   WRITE_REG(CACHEAXIx->CMDREADDRR, addr);  in LL_CACHEAXI_SetEndAddress()
228 __STATIC_INLINE uint32_t LL_CACHEAXI_GetEndAddress(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_GetEndAddress()  argument
230   return (uint32_t)(READ_REG(CACHEAXIx->CMDREADDRR));  in LL_CACHEAXI_GetEndAddress()
244 __STATIC_INLINE void LL_CACHEAXI_SetCommand(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Command)  in LL_CACHEAXI_SetCommand()  argument
247   MODIFY_REG(CACHEAXIx->CR2, CACHEAXI_CR2_CACHECMD, Command);  in LL_CACHEAXI_SetCommand()
259 __STATIC_INLINE uint32_t LL_CACHEAXI_GetCommand(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_GetCommand()  argument
262   return (uint32_t)(READ_BIT(CACHEAXIx->CR2, CACHEAXI_CR2_CACHECMD));  in LL_CACHEAXI_GetCommand()
271 __STATIC_INLINE void LL_CACHEAXI_StartCommand(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_StartCommand()  argument
273   SET_BIT(CACHEAXIx->CR2, CACHEAXI_CR2_STARTCMD);  in LL_CACHEAXI_StartCommand()
282 __STATIC_INLINE void LL_CACHEAXI_Invalidate(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_Invalidate()  argument
284   SET_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_CACHEINV);  in LL_CACHEAXI_Invalidate()
312 __STATIC_INLINE void LL_CACHEAXI_EnableMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)  in LL_CACHEAXI_EnableMonitors()  argument
314   SET_BIT(CACHEAXIx->CR1, Monitors);  in LL_CACHEAXI_EnableMonitors()
333 __STATIC_INLINE void LL_CACHEAXI_DisableMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)  in LL_CACHEAXI_DisableMonitors()  argument
335   CLEAR_BIT(CACHEAXIx->CR1, Monitors);  in LL_CACHEAXI_DisableMonitors()
354 __STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledMonitors(const CACHEAXI_TypeDef *CACHEAXIx, uint32_t …  in LL_CACHEAXI_IsEnabledMonitors()  argument
356 …return (((READ_BIT(CACHEAXIx->CR1, (CACHEAXI_CR1_WMISSMEN | CACHEAXI_CR1_WHITMEN | CACHEAXI_CR1_RM…  in LL_CACHEAXI_IsEnabledMonitors()
379 __STATIC_INLINE void LL_CACHEAXI_ResetMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)  in LL_CACHEAXI_ResetMonitors()  argument
382   SET_BIT(CACHEAXIx->CR1, (Monitors << 2U));  in LL_CACHEAXI_ResetMonitors()
385   CLEAR_BIT(CACHEAXIx->CR1, (Monitors << 2U));  in LL_CACHEAXI_ResetMonitors()
394 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadHitValue(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_Monitor_GetReadHitValue()  argument
396   return CACHEAXIx->RHMONR;  in LL_CACHEAXI_Monitor_GetReadHitValue()
405 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadMissValue(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_Monitor_GetReadMissValue()  argument
407   return CACHEAXIx->RMMONR;  in LL_CACHEAXI_Monitor_GetReadMissValue()
416 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteHitValue(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_Monitor_GetWriteHitValue()  argument
418   return CACHEAXIx->WHMONR;  in LL_CACHEAXI_Monitor_GetWriteHitValue()
427 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteMissValue(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_Monitor_GetWriteMissValue()  argument
429   return CACHEAXIx->WMMONR;  in LL_CACHEAXI_Monitor_GetWriteMissValue()
438 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadAllocMissValue(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_Monitor_GetReadAllocMissValue()  argument
440   return CACHEAXIx->RAMMONR;  in LL_CACHEAXI_Monitor_GetReadAllocMissValue()
449 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteAllocMissValue(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_Monitor_GetWriteAllocMissValue()  argument
451   return CACHEAXIx->WAMMONR;  in LL_CACHEAXI_Monitor_GetWriteAllocMissValue()
460 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteThroughValue(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_Monitor_GetWriteThroughValue()  argument
462   return CACHEAXIx->WTMONR;  in LL_CACHEAXI_Monitor_GetWriteThroughValue()
471 __STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetEvictionValue(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_Monitor_GetEvictionValue()  argument
473   return CACHEAXIx->EVIMONR;  in LL_CACHEAXI_Monitor_GetEvictionValue()
490 __STATIC_INLINE void LL_CACHEAXI_EnableIT_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_EnableIT_BSYEND()  argument
492   SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE);  in LL_CACHEAXI_EnableIT_BSYEND()
501 __STATIC_INLINE void LL_CACHEAXI_DisableIT_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_DisableIT_BSYEND()  argument
503   CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE);  in LL_CACHEAXI_DisableIT_BSYEND()
512 __STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_BSYEND(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_IsEnabledIT_BSYEND()  argument
514   return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE) == (CACHEAXI_IER_BSYENDIE)) ? 1UL : 0UL);  in LL_CACHEAXI_IsEnabledIT_BSYEND()
523 __STATIC_INLINE void LL_CACHEAXI_EnableIT_ERR(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_EnableIT_ERR()  argument
525   SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE);  in LL_CACHEAXI_EnableIT_ERR()
534 __STATIC_INLINE void LL_CACHEAXI_DisableIT_ERR(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_DisableIT_ERR()  argument
536   CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE);  in LL_CACHEAXI_DisableIT_ERR()
545 __STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_ERR(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_IsEnabledIT_ERR()  argument
547   return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE) == (CACHEAXI_IER_ERRIE)) ? 1UL : 0UL);  in LL_CACHEAXI_IsEnabledIT_ERR()
556 __STATIC_INLINE void LL_CACHEAXI_EnableIT_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_EnableIT_CMDEND()  argument
558   SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE);  in LL_CACHEAXI_EnableIT_CMDEND()
567 __STATIC_INLINE void LL_CACHEAXI_DisableIT_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_DisableIT_CMDEND()  argument
569   CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE);  in LL_CACHEAXI_DisableIT_CMDEND()
578 __STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_CMDEND(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_IsEnabledIT_CMDEND()  argument
580   return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE) == (CACHEAXI_IER_CMDENDIE)) ? 1UL : 0UL);  in LL_CACHEAXI_IsEnabledIT_CMDEND()
589 __STATIC_INLINE void LL_CACHEAXI_ClearFlag_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_ClearFlag_BSYEND()  argument
591   WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CBSYENDF);  in LL_CACHEAXI_ClearFlag_BSYEND()
600 __STATIC_INLINE void LL_CACHEAXI_ClearFlag_ERR(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_ClearFlag_ERR()  argument
602   WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CERRF);  in LL_CACHEAXI_ClearFlag_ERR()
611 __STATIC_INLINE void LL_CACHEAXI_ClearFlag_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_ClearFlag_CMDEND()  argument
613   WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CCMDENDF);  in LL_CACHEAXI_ClearFlag_CMDEND()
622 __STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BUSY(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_IsActiveFlag_BUSY()  argument
624   return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BUSYF) == (CACHEAXI_SR_BUSYF)) ? 1UL : 0UL);  in LL_CACHEAXI_IsActiveFlag_BUSY()
633 __STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BSYEND(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_IsActiveFlag_BSYEND()  argument
635   return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BSYENDF) == (CACHEAXI_SR_BSYENDF)) ? 1UL : 0UL);  in LL_CACHEAXI_IsActiveFlag_BSYEND()
644 __STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_ERR(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_IsActiveFlag_ERR()  argument
646   return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_ERRF) == (CACHEAXI_SR_ERRF)) ? 1UL : 0UL);  in LL_CACHEAXI_IsActiveFlag_ERR()
655 __STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BUSYCMD(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_IsActiveFlag_BUSYCMD()  argument
657   return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BUSYCMDF) == (CACHEAXI_SR_BUSYCMDF)) ? 1UL : 0UL);  in LL_CACHEAXI_IsActiveFlag_BUSYCMD()
666 __STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_CMDEND(const CACHEAXI_TypeDef *CACHEAXIx)  in LL_CACHEAXI_IsActiveFlag_CMDEND()  argument
668   return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_CMDENDF) == (CACHEAXI_SR_CMDENDF)) ? 1UL : 0UL);  in LL_CACHEAXI_IsActiveFlag_CMDEND()