Lines Matching refs:Periphs
879 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
882 WRITE_REG(RCC->AHB1ENSR, Periphs); in LL_AHB1_GRP1_EnableClock()
897 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
899 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClock()
911 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
913 WRITE_REG(RCC->AHB1ENCR, Periphs); in LL_AHB1_GRP1_DisableClock()
925 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
927 WRITE_REG(RCC->AHB1RSTSR, Periphs); in LL_AHB1_GRP1_ForceReset()
939 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
941 WRITE_REG(RCC->AHB1RSTCR, Periphs); in LL_AHB1_GRP1_ReleaseReset()
953 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) in LL_AHB1_GRP1_EnableClockLowPower() argument
956 WRITE_REG(RCC->AHB1LPENSR, Periphs); in LL_AHB1_GRP1_EnableClockLowPower()
971 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockLowPower(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClockLowPower() argument
973 return ((READ_BIT(RCC->AHB1LPENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB1_GRP1_IsEnabledClockLowPower()
985 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) in LL_AHB1_GRP1_DisableClockLowPower() argument
987 WRITE_REG(RCC->AHB1LPENCR, Periphs); in LL_AHB1_GRP1_DisableClockLowPower()
1009 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) in LL_AHB2_GRP1_EnableClock() argument
1012 WRITE_REG(RCC->AHB2ENSR, Periphs); in LL_AHB2_GRP1_EnableClock()
1029 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB2_GRP1_IsEnabledClock() argument
1031 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB2_GRP1_IsEnabledClock()
1045 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) in LL_AHB2_GRP1_DisableClock() argument
1047 WRITE_REG(RCC->AHB2ENCR, Periphs); in LL_AHB2_GRP1_DisableClock()
1061 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) in LL_AHB2_GRP1_ForceReset() argument
1063 WRITE_REG(RCC->AHB2RSTSR, Periphs); in LL_AHB2_GRP1_ForceReset()
1077 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB2_GRP1_ReleaseReset() argument
1079 WRITE_REG(RCC->AHB2RSTCR, Periphs); in LL_AHB2_GRP1_ReleaseReset()
1093 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) in LL_AHB2_GRP1_EnableClockLowPower() argument
1096 WRITE_REG(RCC->AHB2LPENSR, Periphs); in LL_AHB2_GRP1_EnableClockLowPower()
1113 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockLowPower(uint32_t Periphs) in LL_AHB2_GRP1_IsEnabledClockLowPower() argument
1115 return ((READ_BIT(RCC->AHB2LPENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB2_GRP1_IsEnabledClockLowPower()
1129 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) in LL_AHB2_GRP1_DisableClockLowPower() argument
1131 WRITE_REG(RCC->AHB2LPENCR, Periphs); in LL_AHB2_GRP1_DisableClockLowPower()
1165 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) in LL_AHB3_GRP1_EnableClock() argument
1168 WRITE_REG(RCC->AHB3ENSR, Periphs); in LL_AHB3_GRP1_EnableClock()
1197 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB3_GRP1_IsEnabledClock() argument
1199 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB3_GRP1_IsEnabledClock()
1225 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) in LL_AHB3_GRP1_DisableClock() argument
1227 WRITE_REG(RCC->AHB3ENCR, Periphs); in LL_AHB3_GRP1_DisableClock()
1249 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) in LL_AHB3_GRP1_ForceReset() argument
1251 WRITE_REG(RCC->AHB3RSTSR, Periphs); in LL_AHB3_GRP1_ForceReset()
1273 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB3_GRP1_ReleaseReset() argument
1275 WRITE_REG(RCC->AHB3RSTCR, Periphs); in LL_AHB3_GRP1_ReleaseReset()
1301 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) in LL_AHB3_GRP1_EnableClockLowPower() argument
1304 WRITE_REG(RCC->AHB3LPENSR, Periphs); in LL_AHB3_GRP1_EnableClockLowPower()
1333 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockLowPower(uint32_t Periphs) in LL_AHB3_GRP1_IsEnabledClockLowPower() argument
1335 return ((READ_BIT(RCC->AHB3LPENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB3_GRP1_IsEnabledClockLowPower()
1361 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) in LL_AHB3_GRP1_DisableClockLowPower() argument
1363 WRITE_REG(RCC->AHB3LPENCR, Periphs); in LL_AHB3_GRP1_DisableClockLowPower()
1407 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) in LL_AHB4_GRP1_EnableClock() argument
1410 WRITE_REG(RCC->AHB4ENSR, Periphs); in LL_AHB4_GRP1_EnableClock()
1449 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB4_GRP1_IsEnabledClock() argument
1451 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB4_GRP1_IsEnabledClock()
1487 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) in LL_AHB4_GRP1_DisableClock() argument
1489 WRITE_REG(RCC->AHB4ENCR, Periphs); in LL_AHB4_GRP1_DisableClock()
1525 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) in LL_AHB4_GRP1_ForceReset() argument
1527 WRITE_REG(RCC->AHB4RSTSR, Periphs); in LL_AHB4_GRP1_ForceReset()
1563 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB4_GRP1_ReleaseReset() argument
1565 WRITE_REG(RCC->AHB4RSTCR, Periphs); in LL_AHB4_GRP1_ReleaseReset()
1601 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockLowPower(uint32_t Periphs) in LL_AHB4_GRP1_EnableClockLowPower() argument
1604 WRITE_REG(RCC->AHB4LPENSR, Periphs); in LL_AHB4_GRP1_EnableClockLowPower()
1643 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockLowPower(uint32_t Periphs) in LL_AHB4_GRP1_IsEnabledClockLowPower() argument
1645 return ((READ_BIT(RCC->AHB4LPENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB4_GRP1_IsEnabledClockLowPower()
1681 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockLowPower(uint32_t Periphs) in LL_AHB4_GRP1_DisableClockLowPower() argument
1683 WRITE_REG(RCC->AHB4LPENCR, Periphs); in LL_AHB4_GRP1_DisableClockLowPower()
1755 __STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs) in LL_AHB5_GRP1_EnableClock() argument
1758 WRITE_REG(RCC->AHB5ENSR, Periphs); in LL_AHB5_GRP1_EnableClock()
1825 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB5_GRP1_IsEnabledClock() argument
1827 return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB5_GRP1_IsEnabledClock()
1891 __STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs) in LL_AHB5_GRP1_DisableClock() argument
1893 WRITE_REG(RCC->AHB5ENCR, Periphs); in LL_AHB5_GRP1_DisableClock()
1945 __STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs) in LL_AHB5_GRP1_ForceReset() argument
1947 WRITE_REG(RCC->AHB5RSTSR, Periphs); in LL_AHB5_GRP1_ForceReset()
1999 __STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB5_GRP1_ReleaseReset() argument
2001 WRITE_REG(RCC->AHB5RSTCR, Periphs); in LL_AHB5_GRP1_ReleaseReset()
2065 __STATIC_INLINE void LL_AHB5_GRP1_EnableClockLowPower(uint32_t Periphs) in LL_AHB5_GRP1_EnableClockLowPower() argument
2068 WRITE_REG(RCC->AHB5LPENSR, Periphs); in LL_AHB5_GRP1_EnableClockLowPower()
2135 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClockLowPower(uint32_t Periphs) in LL_AHB5_GRP1_IsEnabledClockLowPower() argument
2137 return ((READ_BIT(RCC->AHB5LPENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_AHB5_GRP1_IsEnabledClockLowPower()
2201 __STATIC_INLINE void LL_AHB5_GRP1_DisableClockLowPower(uint32_t Periphs) in LL_AHB5_GRP1_DisableClockLowPower() argument
2203 WRITE_REG(RCC->AHB5LPENCR, Periphs); in LL_AHB5_GRP1_DisableClockLowPower()
2273 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) in LL_APB1_GRP1_EnableClock() argument
2276 WRITE_REG(RCC->APB1ENSR1, Periphs); in LL_APB1_GRP1_EnableClock()
2341 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_APB1_GRP1_IsEnabledClock() argument
2343 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB1_GRP1_IsEnabledClock()
2403 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) in LL_APB1_GRP1_DisableClock() argument
2405 WRITE_REG(RCC->APB1ENCR1, Periphs); in LL_APB1_GRP1_DisableClock()
2465 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) in LL_APB1_GRP1_ForceReset() argument
2467 WRITE_REG(RCC->APB1RSTSR1, Periphs); in LL_APB1_GRP1_ForceReset()
2527 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_APB1_GRP1_ReleaseReset() argument
2529 WRITE_REG(RCC->APB1RSTCR1, Periphs); in LL_APB1_GRP1_ReleaseReset()
2591 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) in LL_APB1_GRP1_EnableClockLowPower() argument
2594 WRITE_REG(RCC->APB1LPENSR1, Periphs); in LL_APB1_GRP1_EnableClockLowPower()
2659 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockLowPower(uint32_t Periphs) in LL_APB1_GRP1_IsEnabledClockLowPower() argument
2661 return ((READ_BIT(RCC->APB1LPENR1, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB1_GRP1_IsEnabledClockLowPower()
2723 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) in LL_APB1_GRP1_DisableClockLowPower() argument
2725 WRITE_REG(RCC->APB1LPENCR1, Periphs); in LL_APB1_GRP1_DisableClockLowPower()
2739 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) in LL_APB1_GRP2_EnableClock() argument
2742 WRITE_REG(RCC->APB1ENSR2, Periphs); in LL_APB1_GRP2_EnableClock()
2759 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) in LL_APB1_GRP2_IsEnabledClock() argument
2761 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB1_GRP2_IsEnabledClock()
2775 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) in LL_APB1_GRP2_DisableClock() argument
2777 WRITE_REG(RCC->APB1ENCR2, Periphs); in LL_APB1_GRP2_DisableClock()
2791 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) in LL_APB1_GRP2_ForceReset() argument
2793 WRITE_REG(RCC->APB1RSTSR2, Periphs); in LL_APB1_GRP2_ForceReset()
2807 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) in LL_APB1_GRP2_ReleaseReset() argument
2809 WRITE_REG(RCC->APB1RSTCR2, Periphs); in LL_APB1_GRP2_ReleaseReset()
2823 __STATIC_INLINE void LL_APB1_GRP2_EnableClockLowPower(uint32_t Periphs) in LL_APB1_GRP2_EnableClockLowPower() argument
2826 WRITE_REG(RCC->APB1LPENSR2, Periphs); in LL_APB1_GRP2_EnableClockLowPower()
2843 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockLowPower(uint32_t Periphs) in LL_APB1_GRP2_IsEnabledClockLowPower() argument
2845 return ((READ_BIT(RCC->APB1LPENR2, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB1_GRP2_IsEnabledClockLowPower()
2859 __STATIC_INLINE void LL_APB1_GRP2_DisableClockLowPower(uint32_t Periphs) in LL_APB1_GRP2_DisableClockLowPower() argument
2861 WRITE_REG(RCC->APB1LPENCR2, Periphs); in LL_APB1_GRP2_DisableClockLowPower()
2909 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) in LL_APB2_GRP1_EnableClock() argument
2912 WRITE_REG(RCC->APB2ENSR, Periphs); in LL_APB2_GRP1_EnableClock()
2955 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) in LL_APB2_GRP1_IsEnabledClock() argument
2957 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB2_GRP1_IsEnabledClock()
2997 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) in LL_APB2_GRP1_DisableClock() argument
2999 WRITE_REG(RCC->APB2ENCR, Periphs); in LL_APB2_GRP1_DisableClock()
3039 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) in LL_APB2_GRP1_ForceReset() argument
3041 WRITE_REG(RCC->APB2RSTSR, Periphs); in LL_APB2_GRP1_ForceReset()
3081 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) in LL_APB2_GRP1_ReleaseReset() argument
3083 WRITE_REG(RCC->APB2RSTCR, Periphs); in LL_APB2_GRP1_ReleaseReset()
3123 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) in LL_APB2_GRP1_EnableClockLowPower() argument
3126 WRITE_REG(RCC->APB2LPENSR, Periphs); in LL_APB2_GRP1_EnableClockLowPower()
3169 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockLowPower(uint32_t Periphs) in LL_APB2_GRP1_IsEnabledClockLowPower() argument
3171 return ((READ_BIT(RCC->APB2LPENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB2_GRP1_IsEnabledClockLowPower()
3211 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) in LL_APB2_GRP1_DisableClockLowPower() argument
3213 WRITE_REG(RCC->APB2LPENCR, Periphs); in LL_APB2_GRP1_DisableClockLowPower()
3251 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs) in LL_APB4_GRP1_EnableClock() argument
3254 WRITE_REG(RCC->APB4ENSR1, Periphs); in LL_APB4_GRP1_EnableClock()
3287 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs) in LL_APB4_GRP1_IsEnabledClock() argument
3289 return ((READ_BIT(RCC->APB4ENR1, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB4_GRP1_IsEnabledClock()
3319 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs) in LL_APB4_GRP1_DisableClock() argument
3321 WRITE_REG(RCC->APB4ENCR1, Periphs); in LL_APB4_GRP1_DisableClock()
3349 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs) in LL_APB4_GRP1_ForceReset() argument
3351 WRITE_REG(RCC->APB4RSTSR1, Periphs); in LL_APB4_GRP1_ForceReset()
3379 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs) in LL_APB4_GRP1_ReleaseReset() argument
3381 WRITE_REG(RCC->APB4RSTCR1, Periphs); in LL_APB4_GRP1_ReleaseReset()
3411 __STATIC_INLINE void LL_APB4_GRP1_EnableClockLowPower(uint32_t Periphs) in LL_APB4_GRP1_EnableClockLowPower() argument
3414 WRITE_REG(RCC->APB4LPENSR1, Periphs); in LL_APB4_GRP1_EnableClockLowPower()
3447 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClockLowPower(uint32_t Periphs) in LL_APB4_GRP1_IsEnabledClockLowPower() argument
3449 return ((READ_BIT(RCC->APB4LPENR1, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB4_GRP1_IsEnabledClockLowPower()
3479 __STATIC_INLINE void LL_APB4_GRP1_DisableClockLowPower(uint32_t Periphs) in LL_APB4_GRP1_DisableClockLowPower() argument
3481 WRITE_REG(RCC->APB4LPENCR1, Periphs); in LL_APB4_GRP1_DisableClockLowPower()
3495 __STATIC_INLINE void LL_APB4_GRP2_EnableClock(uint32_t Periphs) in LL_APB4_GRP2_EnableClock() argument
3498 WRITE_REG(RCC->APB4ENSR2, Periphs); in LL_APB4_GRP2_EnableClock()
3515 __STATIC_INLINE uint32_t LL_APB4_GRP2_IsEnabledClock(uint32_t Periphs) in LL_APB4_GRP2_IsEnabledClock() argument
3517 return ((READ_BIT(RCC->APB4ENR2, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB4_GRP2_IsEnabledClock()
3531 __STATIC_INLINE void LL_APB4_GRP2_DisableClock(uint32_t Periphs) in LL_APB4_GRP2_DisableClock() argument
3533 WRITE_REG(RCC->APB4ENCR2, Periphs); in LL_APB4_GRP2_DisableClock()
3545 __STATIC_INLINE void LL_APB4_GRP2_ForceReset(uint32_t Periphs) in LL_APB4_GRP2_ForceReset() argument
3547 WRITE_REG(RCC->APB4RSTSR2, Periphs); in LL_APB4_GRP2_ForceReset()
3559 __STATIC_INLINE void LL_APB4_GRP2_ReleaseReset(uint32_t Periphs) in LL_APB4_GRP2_ReleaseReset() argument
3561 WRITE_REG(RCC->APB4RSTCR2, Periphs); in LL_APB4_GRP2_ReleaseReset()
3575 __STATIC_INLINE void LL_APB4_GRP2_EnableClockLowPower(uint32_t Periphs) in LL_APB4_GRP2_EnableClockLowPower() argument
3578 WRITE_REG(RCC->APB4LPENSR2, Periphs); in LL_APB4_GRP2_EnableClockLowPower()
3595 __STATIC_INLINE uint32_t LL_APB4_GRP2_IsEnabledClockLowPower(uint32_t Periphs) in LL_APB4_GRP2_IsEnabledClockLowPower() argument
3597 return ((READ_BIT(RCC->APB4LPENR2, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB4_GRP2_IsEnabledClockLowPower()
3611 __STATIC_INLINE void LL_APB4_GRP2_DisableClockLowPower(uint32_t Periphs) in LL_APB4_GRP2_DisableClockLowPower() argument
3613 WRITE_REG(RCC->APB4LPENCR2, Periphs); in LL_APB4_GRP2_DisableClockLowPower()
3639 __STATIC_INLINE void LL_APB5_GRP1_EnableClock(uint32_t Periphs) in LL_APB5_GRP1_EnableClock() argument
3642 WRITE_REG(RCC->APB5ENSR, Periphs); in LL_APB5_GRP1_EnableClock()
3663 __STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs) in LL_APB5_GRP1_IsEnabledClock() argument
3665 return ((READ_BIT(RCC->APB5ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB5_GRP1_IsEnabledClock()
3683 __STATIC_INLINE void LL_APB5_GRP1_DisableClock(uint32_t Periphs) in LL_APB5_GRP1_DisableClock() argument
3685 WRITE_REG(RCC->APB5ENCR, Periphs); in LL_APB5_GRP1_DisableClock()
3703 __STATIC_INLINE void LL_APB5_GRP1_ForceReset(uint32_t Periphs) in LL_APB5_GRP1_ForceReset() argument
3705 WRITE_REG(RCC->APB5RSTSR, Periphs); in LL_APB5_GRP1_ForceReset()
3723 __STATIC_INLINE void LL_APB5_GRP1_ReleaseReset(uint32_t Periphs) in LL_APB5_GRP1_ReleaseReset() argument
3725 WRITE_REG(RCC->APB5RSTCR, Periphs); in LL_APB5_GRP1_ReleaseReset()
3743 __STATIC_INLINE void LL_APB5_GRP1_EnableClockLowPower(uint32_t Periphs) in LL_APB5_GRP1_EnableClockLowPower() argument
3746 WRITE_REG(RCC->APB5LPENSR, Periphs); in LL_APB5_GRP1_EnableClockLowPower()
3767 __STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClockLowPower(uint32_t Periphs) in LL_APB5_GRP1_IsEnabledClockLowPower() argument
3769 return ((READ_BIT(RCC->APB5LPENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB5_GRP1_IsEnabledClockLowPower()
3787 __STATIC_INLINE void LL_APB5_GRP1_DisableClockLowPower(uint32_t Periphs) in LL_APB5_GRP1_DisableClockLowPower() argument
3789 WRITE_REG(RCC->APB5LPENCR, Periphs); in LL_APB5_GRP1_DisableClockLowPower()