Lines Matching full:with
14 * If no LICENSE file comes with this software, it is provided AS-IS.
114 … for compatibility with some ADC on other STM32
118 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
126 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
143 … compatibility with some ADC on other STM32 series
147 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
155 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
377 … | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
396 … In case of usage with HAL driver, refer to HAL_BSEC_OTP_Reload() */
398 with which VrefInt has been calibrated in production
485 (for devices with several ADC instances).
518 * (setting possible with ADC enabled without conversion on going,
519 * ADC enabled with conversion on going, ...)
520 * Each feature can be updated afterwards with a unitary function
521 * and potentially with ADC in a different state than disabled,
532 …Shift; /*!< Configures the left shifting applied to the final result with or without
548 * (functions with prefix "REG").
555 * (setting possible with ADC enabled without conversion on going,
556 * ADC enabled with conversion on going, ...)
557 * Each feature can be updated afterwards with a unitary function
558 * and potentially with ADC in a different state than disabled,
569 … with some ADC on other STM32 series having this setting set by HW
618 * (functions with prefix "INJ").
625 * (setting possible with ADC enabled without conversion on going,
626 * ADC enabled with conversion on going, ...)
627 * Each feature can be updated afterwards with a unitary function
628 * and potentially with ADC in a different state than disabled,
639 … compatibility with some ADC on other STM32 series having this
680 * @brief Flags defines which can be used with LL_ADC_ReadReg function
742 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
765 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
768 /* List of ADC registers intended to be used (most commonly) with */
772 … (corresponding to register DR) to be used with ADC configured in independent
777 … to be used with ADC configured in multimode (available on STM32 devices
778 with several ADC instances), without data packing.
779 … Register used is CDR2, compliant with all ADC multimode data format
785 … to be used with ADC configured in multimode (available on STM32 devices
786 with several ADC instances), with data packing.
867 … See description with function @ref LL_ADC_SetLPModeAutoWait(). */
871 /* Definitions for backward compatibility with legacy STM32 series */
1180 … This ADC mode is intended to be used with DMA mode non-circular. */
1185 … This ADC mode is intended to be used with DMA mode circular. */
1208 with 2 ranks in the sequence */
1210 with 3 ranks in the sequence */
1212 with 4 ranks in the sequence */
1214 with 5 ranks in the sequence */
1216 with 6 ranks in the sequence */
1218 with 7 ranks in the sequence */
1221 with 8 ranks in the sequence */
1223 with 9 ranks in the sequence */
1225 with 10 ranks in the sequence */
1227 with 11 ranks in the sequence */
1230 with 12 ranks in the sequence */
1232 with 13 ranks in the sequence */
1235 with 14 ranks in the sequence */
1238 with 15 ranks in the sequence */
1241 with 16 ranks in the sequence */
1252 … discontinuous mode enable with sequence interruption every rank */
1254 … discontinuous mode enabled with sequence interruption every 2 ranks */
1256 … discontinuous mode enable with sequence interruption every 3 ranks */
1259 … discontinuous mode enable with sequence interruption every 4 ranks */
1261 … discontinuous mode enable with sequence interruption every 5 ranks */
1264 … discontinuous mode enable with sequence interruption every 6 ranks */
1267 … discontinuous mode enable with sequence interruption every 7 ranks */
1270 … discontinuous mode enable with sequence interruption every 8 ranks */
1444 … regular. Setting compliant only with group injected trigger source set to
1457 …C_INJ_SEQ_SCAN_ENABLE_2RANKS (ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks
1459 …C_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1) /*!< ADC group injected sequencer enable with 3 ranks
1462 … | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks
1474 enable with sequence interruption every rank */
1919 … alternate trigger. Works only with external triggers (not SW start) */
1936 with its individual DMA transfer settings. */
1939 … (CDR, CDR2) with packing option on 32 bit. In register CDR,
1942 … must be lower than 16 bit (even with ADC resolution 12 bit,
1946 … In case of usage with DMA, CDR generate ones transfer request
1950 … (CDR, CDR2) with packing option on 16 bit. In register CDR,
1953 must be lower than 8 bit (even with ADC resolution 8 bit,
1957 … In case of usage with DMA, CDR generate ones transfer request
2118 * number is returned, either defined with number
2119 * or with bitfield (only one bit must be set).
2187 * comparison with internal channel parameter to be done
2206 * number in ADC registers. The differentiation is made only with
2313 * number in ADC registers. The differentiation is made only with
2395 * comparison with internal channel parameter to be done
2403 * define a single channel to monitor with analog watchdog
2405 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2438 * comparison with internal channel parameter to be done
2544 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
2545 * Example, with a ADC resolution of 8 bits, to set the value of
2567 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2568 * Example, with a ADC resolution of 8 bits, to get the value of
2586 * @brief Helper macro to set the ADC calibration value with both single ended
2588 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2604 * or ADC slave from raw value with both ADC conversion data concatenated.
2607 * In this case the transferred data need to processed with this macro
2624 * @note In case of device with multimode available and a mix of
2625 * ADC instances compliant and not compliant with multimode feature,
2626 * ADC instances not compliant with multimode feature are
2646 * - Multimode (for devices with several ADC instances)
2656 * @note This check is required by functions with setting conditioned to
2660 * @note On devices with only 1 ADC common instance, parameter of this macro
2662 * with devices featuring several ADC common instances).
2788 * intended to be used (most commonly) with DMA transfer.
2792 * @note This macro is intended to be used with LL DMA driver, refer to
2800 * @note For devices with several ADC: in multimode, some devices
2813 * (1) Available on devices with several ADC instances.
2875 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2913 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2941 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3090 * or differential (for devices with differential mode available).
3122 * or differential (for devices with differential mode available).
3125 * @note For devices with differential mode available:
3138 /* Retrieve bits with position in register depending on parameter */ in LL_ADC_GetCalibrationFactor()
3140 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ in LL_ADC_GetCalibrationFactor()
3203 * - It is not recommended to use with interruption or DMA
3209 * - Do use with polling: 1. Start conversion,
3218 * (with startup time between trigger and start of sampling).
3219 * This feature can be combined with low power mode "auto wait".
3220 * @note With ADC low power mode "auto wait", the ADC conversion data read
3259 * - It is not recommended to use with interruption or DMA
3265 * - Do use with polling: 1. Start conversion,
3274 * (with startup time between trigger and start of sampling).
3275 * This feature can be combined with low power mode "auto wait".
3276 * @note With ADC low power mode "auto wait", the ADC conversion data read
3299 * with the lowest value is considered for the subtraction.
3361 * with parts of literals LL_ADC_CHANNEL_x or using
3366 * process the returned value with the helper macro
3406 * comparison with internal channel parameter to be done
3647 * 1 -> 16393 Gain compensation will be enabled with specified value
3663 * 1 -> 16393 Gain compensation is enabled with returned value
3685 * (default setting for compatibility with some ADC on other
3784 /* to match with triggers literals definition. */ in LL_ADC_REG_GetTriggerSource()
3925 * - For devices with sequencer fully configurable
3935 * - For devices with sequencer not fully configurable
3984 * - For devices with sequencer fully configurable
3994 * - For devices with sequencer not fully configurable
4175 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_REG_SetSequencerRanks()
4177 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_REG_SetSequencerRanks()
4200 * with parts of literals LL_ADC_CHANNEL_x or using
4205 * process the returned value with the helper macro
4269 * comparison with internal channel parameter to be done
4424 * @note Compatibility with devices without feature overrun:
4428 * Therefore, for compatibility with all devices, parameter
4474 * (default setting for compatibility with some ADC on other
4482 * ADC must not be disabled. Can be enabled with or without conversion
4571 /* to match with triggers literals definition. */ in LL_ADC_INJ_GetTriggerSource()
4599 * ADC must not be disabled. Can be enabled with or without conversion
4639 * ADC must not be disabled. Can be enabled with or without conversion
4720 * ADC must not be disabled. Can be enabled with or without conversion
4763 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_INJ_SetSequencerRanks()
4765 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_INJ_SetSequencerRanks()
4782 * with parts of literals LL_ADC_CHANNEL_x or using
4787 * process the returned value with the helper macro
4827 * comparison with internal channel parameter to be done
4842 * updated after one ADC conversion trigger and with data
4850 * ADC group injected automatic trigger is compliant only with
4981 /* Set bits with content of parameter "SamplingTime" with bits position */ in LL_ADC_SetChannelSamplingTime()
4983 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_SetChannelSamplingTime()
5055 * comparison with internal channel parameter to be done
5217 * with analog watchdog from sequencer channel definition,
5331 /* Set bits with content of parameter "AWDChannelGroup" with bits position */ in LL_ADC_SetAnalogWDMonitChannels()
5333 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ in LL_ADC_SetAnalogWDMonitChannels()
5351 * with parts of literals LL_ADC_CHANNEL_x or using
5356 * process the returned value with the helper macro
5565 * ADC can be disabled, enabled with or without conversion on going
5589 /* Set bits with content of parameter "AWDThresholdValue" with bits */ in LL_ADC_SetAnalogWDThresholds()
5592 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ in LL_ADC_SetAnalogWDThresholds()
5610 * threshold low or raw data with ADC thresholds high and low
5895 * or multimode (for devices with several ADC instances).
5902 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5926 * or multimode (for devices with several ADC instances).
5957 * Conversion data is a raw data with ADC master and slave
5989 * Conversion data is a raw data with ADC master and slave
6017 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6092 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_EnableDeepPowerDown()
6094 /* to not interfere with bits with HW property "rs". */ in LL_ADC_EnableDeepPowerDown()
6115 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_DisableDeepPowerDown()
6117 /* to not interfere with bits with HW property "rs". */ in LL_ADC_DisableDeepPowerDown()
6151 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Enable()
6153 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Enable()
6171 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Disable()
6173 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Disable()
6206 * or differential (for devices with differential mode available).
6210 * @note For devices with differential mode available:
6229 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_StartCalibration()
6231 /* to not interfere with bits with HW property "rs". */ in LL_ADC_StartCalibration()
6260 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_StopCalibration()
6262 /* to not interfere with bits with HW property "rs". */ in LL_ADC_StopCalibration()
6326 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StartConversion()
6328 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StartConversion()
6338 * ADC must be enabled with conversion on going on group regular,
6346 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StopConversion()
6348 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StopConversion()
6380 * with feature oversampling).
6393 * @note For devices with feature oversampling: Oversampling
6408 * @note For devices with feature oversampling: Oversampling
6423 * @note For devices with feature oversampling: Oversampling
6438 * @note For devices with feature oversampling: Oversampling
6457 * @note From raw data with ADC master and slave concatenated,
6475 * @note Multimode data without concatenation is compliant with all
6522 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StartConversion()
6524 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StartConversion()
6534 * ADC must be enabled with conversion on going on group injected,
6542 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StopConversion()
6544 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StopConversion()
6576 * with feature oversampling).
6602 * @note For devices with feature oversampling: Oversampling
6630 * @note For devices with feature oversampling: Oversampling
6658 * @note For devices with feature oversampling: Oversampling
6686 * @note For devices with feature oversampling: Oversampling