Lines Matching full:mode
54 uint32_t MemoryMode; /*!< It Specifies the memory mode.
140 used for memory-mapped mode).
146 uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
150 uint32_t InstructionDTRMode; /*!< It enables or not the DTR mode for the instruction phase.
154 …uint32_t AddressMode; /*!< It indicates the address mode. Address mode precises numb…
159 uint32_t AddressDTRMode; /*!< It enables or not the DTR mode for the address phase.
163 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
167 …uint32_t AlternateBytesDTRMode; /*!< It enables or not the DTR mode for the alternate bytes ph…
169 …uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of …
173 This field is only used for indirect mode.
175 uint32_t DataDTRMode; /*!< It enables or not the DTR mode for the data phase.
193 uint32_t LatencyMode; /*!< It configures the latency mode.
209 This field is only used for indirect mode.
211 In case of autopolling mode, this parameter can be
215 …uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of …
221 * @brief HAL XSPI Auto Polling mode configuration structure definition
240 * @brief HAL XSPI Memory Mapped mode configuration structure definition
327 …HYPERBUS_INIT (0x00000001U) /*!< Initialization done in hyperbus mode but timing configur…
358 /** @defgroup XSPI_MemoryMode XSPI Memory Mode
361 #define HAL_XSPI_SINGLE_MEM (0x00000000U) /*!< Dual-memory mode disabled */
362 #define HAL_XSPI_DUAL_MEM (XSPI_CR_DMM) /*!< Dual mode enabled */
371 …L_XSPI_MEMTYPE_MICRON (0x00000000U) /*!< Micron mode */
372 …L_XSPI_MEMTYPE_MACRONIX (XSPI_DCR1_MTYP_0) /*!< Macronix mode */
373 …L_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory mode */
374 …L_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/
375 …L_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
376 …L_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode */
430 /** @defgroup XSPI_ClockMode XSPI Clock Mode
529 …PE_COMMON_CFG (0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */
530 …PE_READ_CFG (0x00000001U) /*!< Read configuration (memory-mapped mode) */
531 …PE_WRITE_CFG (0x00000002U) /*!< Write configuration (memory-mapped mode) */
532 …PE_WRAP_CFG (0x00000003U) /*!< Wrap configuration (memory-mapped mode) */
551 /** @defgroup XSPI_InstructionMode XSPI Instruction Mode
574 /** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode
577 #define HAL_XSPI_INSTRUCTION_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for …
578 #define HAL_XSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)XSPI_CCR_IDTR) /*!< DTR mode enabled for i…
583 /** @defgroup XSPI_AddressMode XSPI Address Mode
606 /** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode
609 #define HAL_XSPI_ADDRESS_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for…
610 #define HAL_XSPI_ADDRESS_DTR_ENABLE ((uint32_t)XSPI_CCR_ADDTR) /*!< DTR mode enabled for …
615 /** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode
638 /** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode
641 #define HAL_XSPI_ALT_BYTES_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for…
642 #define HAL_XSPI_ALT_BYTES_DTR_ENABLE ((uint32_t)XSPI_CCR_ABDTR) /*!< DTR mode enabled for …
647 /** @defgroup XSPI_DataMode XSPI Data Mode
660 /** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode
663 #define HAL_XSPI_DATA_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for …
664 #define HAL_XSPI_DATA_DTR_ENABLE ((uint32_t)XSPI_CCR_DDTR) /*!< DTR mode enabled for d…
669 /** @defgroup XSPI_DQSMode XSPI DQS Mode
687 /** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode
699 …e HAL_XSPI_MEMORY_ADDRESS_SPACE (0x00000000U) /*!< HyperBus memory mode */
700 …e HAL_XSPI_REGISTER_ADDRESS_SPACE ((uint32_t)XSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
705 /** @defgroup XSPI_MatchMode XSPI Match Mode
708 #define HAL_XSPI_MATCH_MODE_AND (0x00000000U) /*!< AND match mode between u…
709 #define HAL_XSPI_MATCH_MODE_OR ((uint32_t)XSPI_CR_PMM) /*!< OR match mode between un…
754 … XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode …
755 …SPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode …
798 …A_OUTPUT_DELAY (0x00000002U) /*!< Delay value for output data in DDR mode for write operation…
963 /* XSPI indirect mode functions */
971 /* XSPI status flag polling mode functions */
976 /* XSPI memory-mapped mode functions */
984 /* XSPI indirect mode Callback functions */
991 /* XSPI status flag polling mode functions */
994 /* XSPI memory-mapped mode functions */
1059 #define IS_XSPI_MEMORY_MODE(MODE) (((MODE) == HAL_XSPI_SINGLE_MEM) || \ argument
1060 ((MODE) == HAL_XSPI_DUAL_MEM))
1107 #define IS_XSPI_CLOCK_MODE(MODE) (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \ argument
1108 ((MODE) == HAL_XSPI_CLOCK_MODE_3))
1180 #define IS_XSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_NONE) || \ argument
1181 ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE) || \
1182 ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \
1183 ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \
1184 ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES))
1191 #define IS_XSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \ argument
1192 ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE))
1194 #define IS_XSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_NONE) || \ argument
1195 ((MODE) == HAL_XSPI_ADDRESS_1_LINE) || \
1196 ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \
1197 ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \
1198 ((MODE) == HAL_XSPI_ADDRESS_8_LINES))
1205 #define IS_XSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \ argument
1206 ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE))
1208 #define IS_XSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_NONE) || \ argument
1209 ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE) || \
1210 ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \
1211 ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \
1212 ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES))
1219 #define IS_XSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \ argument
1220 ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE))
1222 #define IS_XSPI_DATA_MODE(TYPE,MODE) (((TYPE) == (HAL_XSPI_MEMTYPE_HYPERBUS)) ? \ argument
1223 (((MODE) == HAL_XSPI_DATA_NONE) || \
1224 ((MODE) == HAL_XSPI_DATA_8_LINES) || \
1225 ((MODE) == HAL_XSPI_DATA_16_LINES)): \
1226 (((MODE) == HAL_XSPI_DATA_NONE) || \
1227 ((MODE) == HAL_XSPI_DATA_1_LINE) || \
1228 ((MODE) == HAL_XSPI_DATA_2_LINES) || \
1229 ((MODE) == HAL_XSPI_DATA_4_LINES) || \
1230 ((MODE) == HAL_XSPI_DATA_8_LINES) || \
1231 ((MODE) == HAL_XSPI_DATA_16_LINES)))
1234 #define IS_XSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \ argument
1235 ((MODE) == HAL_XSPI_DATA_DTR_ENABLE))
1239 #define IS_XSPI_DQS_MODE(MODE) (((MODE) == HAL_XSPI_DQS_DISABLE) || \ argument
1240 ((MODE) == HAL_XSPI_DQS_ENABLE))
1246 #define IS_XSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \ argument
1247 ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE))
1249 #define IS_XSPI_LATENCY_MODE(MODE) (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \ argument
1250 ((MODE) == HAL_XSPI_FIXED_LATENCY))
1255 #define IS_XSPI_MATCH_MODE(MODE) (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \ argument
1256 ((MODE) == HAL_XSPI_MATCH_MODE_OR))
1258 #define IS_XSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \ argument
1259 ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE))
1265 #define IS_XSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \ argument
1266 ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE))
1267 #define IS_XSPI_NO_PREFETCH_DATA(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_PREFETCH_ENABLE) |… argument
1268 ((MODE) == HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE))
1270 #define IS_XSPI_NO_PREFETCH_AXI(MODE) (((MODE) == HAL_XSPI_AXI_PREFETCH_ENABLE) || \ argument
1271 ((MODE) == HAL_XSPI_AXI_PREFETCH_DISABLE))