Lines Matching refs:CCER

567   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
573 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_ENCODER_Init()
600 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_ENCODER_Init()
654 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_HALLSENSOR_Init()
663 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_HALLSENSOR_Init()
704 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_HALLSENSOR_Init()
839 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); in OC1Config()
842 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC1Config()
890 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC1Config()
918 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); in OC2Config()
921 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC2Config()
969 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC2Config()
997 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); in OC3Config()
1000 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC3Config()
1048 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC3Config()
1076 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); in OC4Config()
1079 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC4Config()
1118 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC4Config()
1145 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); in OC5Config()
1148 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC5Config()
1179 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC5Config()
1206 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); in OC6Config()
1209 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC6Config()
1239 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC6Config()
1262 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; in IC1Config()
1270 MODIFY_REG(TIMx->CCER, in IC1Config()
1295 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; in IC2Config()
1303 MODIFY_REG(TIMx->CCER, in IC2Config()
1328 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; in IC3Config()
1336 MODIFY_REG(TIMx->CCER, in IC3Config()
1361 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; in IC4Config()
1369 MODIFY_REG(TIMx->CCER, in IC4Config()