158 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)  in FMC_NORSRAM_Init()  argument
163   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Init()
182   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);  in FMC_NORSRAM_Init()
194   MODIFY_REG(Device->BTCR[Init->NSBank],  in FMC_NORSRAM_Init()
230     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);  in FMC_NORSRAM_Init()
240     MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime));  in FMC_NORSRAM_Init()
246         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);  in FMC_NORSRAM_Init()
250         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);  in FMC_NORSRAM_Init()
254         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);  in FMC_NORSRAM_Init()
258         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);  in FMC_NORSRAM_Init()
276 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExD…  in FMC_NORSRAM_DeInit()  argument
279   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_DeInit()
284   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
290     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
295     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
298   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
305         CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);  in FMC_NORSRAM_DeInit()
309         CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);  in FMC_NORSRAM_DeInit()
313         CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);  in FMC_NORSRAM_DeInit()
317         CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);  in FMC_NORSRAM_DeInit()
335 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *T…  in FMC_NORSRAM_Timing_Init()  argument
340   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Timing_Init()
352 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                     …  in FMC_NORSRAM_Timing_Init()
362   if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))  in FMC_NORSRAM_Timing_Init()
364 …tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTR1_CLKDIV_Pos…  in FMC_NORSRAM_Timing_Init()
366     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr);  in FMC_NORSRAM_Timing_Init()
384 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRA…  in FMC_NORSRAM_Extended_Timing_Init()  argument
393     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));  in FMC_NORSRAM_Extended_Timing_Init()
405 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
418     Device->BWTR[Bank] = 0x000FFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
448 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
451   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Enable()
455   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
466 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
469   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Disable()
473   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()