Lines Matching refs:CCER

2671   tmpccer = htim->Instance->CCER;  in HAL_TIM_Encoder_Init()
2698 htim->Instance->CCER = tmpccer; in HAL_TIM_Encoder_Init()
6001 TIMx->CCER &= ~TIM_CCER_CC1E; in TIM_OC1_SetConfig()
6004 tmpccer = TIMx->CCER; in TIM_OC1_SetConfig()
6060 TIMx->CCER = tmpccer; in TIM_OC1_SetConfig()
6076 TIMx->CCER &= ~TIM_CCER_CC2E; in TIM_OC2_SetConfig()
6079 tmpccer = TIMx->CCER; in TIM_OC2_SetConfig()
6136 TIMx->CCER = tmpccer; in TIM_OC2_SetConfig()
6152 TIMx->CCER &= ~TIM_CCER_CC3E; in TIM_OC3_SetConfig()
6155 tmpccer = TIMx->CCER; in TIM_OC3_SetConfig()
6210 TIMx->CCER = tmpccer; in TIM_OC3_SetConfig()
6226 TIMx->CCER &= ~TIM_CCER_CC4E; in TIM_OC4_SetConfig()
6229 tmpccer = TIMx->CCER; in TIM_OC4_SetConfig()
6270 TIMx->CCER = tmpccer; in TIM_OC4_SetConfig()
6287 TIMx->CCER &= ~TIM_CCER_CC5E; in TIM_OC5_SetConfig()
6290 tmpccer = TIMx->CCER; in TIM_OC5_SetConfig()
6323 TIMx->CCER = tmpccer; in TIM_OC5_SetConfig()
6340 TIMx->CCER &= ~TIM_CCER_CC6E; in TIM_OC6_SetConfig()
6343 tmpccer = TIMx->CCER; in TIM_OC6_SetConfig()
6377 TIMx->CCER = tmpccer; in TIM_OC6_SetConfig()
6439 tmpccer = htim->Instance->CCER; in TIM_SlaveTimer_SetConfig()
6440 htim->Instance->CCER &= ~TIM_CCER_CC1E; in TIM_SlaveTimer_SetConfig()
6449 htim->Instance->CCER = tmpccer; in TIM_SlaveTimer_SetConfig()
6524 TIMx->CCER &= ~TIM_CCER_CC1E; in TIM_TI1_SetConfig()
6526 tmpccer = TIMx->CCER; in TIM_TI1_SetConfig()
6549 TIMx->CCER = tmpccer; in TIM_TI1_SetConfig()
6570 tmpccer = TIMx->CCER; in TIM_TI1_ConfigInputStage()
6571 TIMx->CCER &= ~TIM_CCER_CC1E; in TIM_TI1_ConfigInputStage()
6584 TIMx->CCER = tmpccer; in TIM_TI1_ConfigInputStage()
6614 TIMx->CCER &= ~TIM_CCER_CC2E; in TIM_TI2_SetConfig()
6616 tmpccer = TIMx->CCER; in TIM_TI2_SetConfig()
6632 TIMx->CCER = tmpccer; in TIM_TI2_SetConfig()
6653 TIMx->CCER &= ~TIM_CCER_CC2E; in TIM_TI2_ConfigInputStage()
6655 tmpccer = TIMx->CCER; in TIM_TI2_ConfigInputStage()
6667 TIMx->CCER = tmpccer; in TIM_TI2_ConfigInputStage()
6697 TIMx->CCER &= ~TIM_CCER_CC3E; in TIM_TI3_SetConfig()
6699 tmpccer = TIMx->CCER; in TIM_TI3_SetConfig()
6715 TIMx->CCER = tmpccer; in TIM_TI3_SetConfig()
6745 TIMx->CCER &= ~TIM_CCER_CC4E; in TIM_TI4_SetConfig()
6747 tmpccer = TIMx->CCER; in TIM_TI4_SetConfig()
6763 TIMx->CCER = tmpccer ; in TIM_TI4_SetConfig()
6854 TIMx->CCER &= ~tmp; in TIM_CCxChannelCmd()
6857 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ in TIM_CCxChannelCmd()