Lines Matching refs:hqspi
281 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, F…
282 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod…
312 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Init() argument
318 if(hqspi == NULL) in HAL_QSPI_Init()
324 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance)); in HAL_QSPI_Init()
325 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler)); in HAL_QSPI_Init()
326 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
327 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting)); in HAL_QSPI_Init()
328 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); in HAL_QSPI_Init()
329 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); in HAL_QSPI_Init()
330 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); in HAL_QSPI_Init()
331 assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); in HAL_QSPI_Init()
333 if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) in HAL_QSPI_Init()
335 assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); in HAL_QSPI_Init()
339 __HAL_LOCK(hqspi); in HAL_QSPI_Init()
341 if(hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_Init()
344 hqspi->Lock = HAL_UNLOCKED; in HAL_QSPI_Init()
348 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_Init()
349 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_Init()
350 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_Init()
351 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_Init()
352 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_Init()
353 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_Init()
354 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_Init()
355 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_Init()
356 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_Init()
357 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_Init()
359 if(hqspi->MspInitCallback == NULL) in HAL_QSPI_Init()
361 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_Init()
365 hqspi->MspInitCallback(hqspi); in HAL_QSPI_Init()
368 HAL_QSPI_MspInit(hqspi); in HAL_QSPI_Init()
372 HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE); in HAL_QSPI_Init()
376 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_Init()
377 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
380 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Init()
385 …MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUAD… in HAL_QSPI_Init()
386 ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | in HAL_QSPI_Init()
387 hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); in HAL_QSPI_Init()
390 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), in HAL_QSPI_Init()
391 ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | in HAL_QSPI_Init()
392 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); in HAL_QSPI_Init()
395 __HAL_QSPI_ENABLE(hqspi); in HAL_QSPI_Init()
398 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Init()
401 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Init()
405 __HAL_UNLOCK(hqspi); in HAL_QSPI_Init()
416 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_DeInit() argument
419 if(hqspi == NULL) in HAL_QSPI_DeInit()
425 __HAL_LOCK(hqspi); in HAL_QSPI_DeInit()
428 __HAL_QSPI_DISABLE(hqspi); in HAL_QSPI_DeInit()
431 if(hqspi->MspDeInitCallback == NULL) in HAL_QSPI_DeInit()
433 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_DeInit()
437 hqspi->MspDeInitCallback(hqspi); in HAL_QSPI_DeInit()
440 HAL_QSPI_MspDeInit(hqspi); in HAL_QSPI_DeInit()
444 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_DeInit()
447 hqspi->State = HAL_QSPI_STATE_RESET; in HAL_QSPI_DeInit()
450 __HAL_UNLOCK(hqspi); in HAL_QSPI_DeInit()
460 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspInit() argument
463 UNUSED(hqspi); in HAL_QSPI_MspInit()
475 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspDeInit() argument
478 UNUSED(hqspi); in HAL_QSPI_MspDeInit()
514 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_IRQHandler() argument
517 uint32_t flag = READ_REG(hqspi->Instance->SR); in HAL_QSPI_IRQHandler()
518 uint32_t itsource = READ_REG(hqspi->Instance->CR); in HAL_QSPI_IRQHandler()
523 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
525 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
528 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
530 if (hqspi->TxXferCount > 0U) in HAL_QSPI_IRQHandler()
533 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_IRQHandler()
534 hqspi->pTxBuffPtr++; in HAL_QSPI_IRQHandler()
535 hqspi->TxXferCount--; in HAL_QSPI_IRQHandler()
541 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
546 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
549 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
551 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
554 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
555 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
556 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
562 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
574 hqspi->FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
576 HAL_QSPI_FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
584 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); in HAL_QSPI_IRQHandler()
587 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
590 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
592 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
595 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
598 __HAL_MDMA_DISABLE(hqspi->hmdma); in HAL_QSPI_IRQHandler()
603 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
607 hqspi->TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
609 HAL_QSPI_TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
612 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
614 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
617 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
620 __HAL_MDMA_DISABLE(hqspi->hmdma); in HAL_QSPI_IRQHandler()
624 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
625 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) in HAL_QSPI_IRQHandler()
627 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
630 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
631 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
632 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
644 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
648 hqspi->RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
650 HAL_QSPI_RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
653 else if(hqspi->State == HAL_QSPI_STATE_BUSY) in HAL_QSPI_IRQHandler()
656 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
660 hqspi->CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
662 HAL_QSPI_CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
665 else if(hqspi->State == HAL_QSPI_STATE_ABORT) in HAL_QSPI_IRQHandler()
668 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_IRQHandler()
671 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
673 if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE) in HAL_QSPI_IRQHandler()
679 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
681 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
690 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
692 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
706 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); in HAL_QSPI_IRQHandler()
709 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) in HAL_QSPI_IRQHandler()
712 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_IRQHandler()
715 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
720 hqspi->StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
722 HAL_QSPI_StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
730 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); in HAL_QSPI_IRQHandler()
733 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
736 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; in HAL_QSPI_IRQHandler()
738 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
741 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
744 hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_IRQHandler()
745 if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) in HAL_QSPI_IRQHandler()
748 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_IRQHandler()
751 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
755 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
757 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
764 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
768 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
770 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
779 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); in HAL_QSPI_IRQHandler()
783 hqspi->TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
785 HAL_QSPI_TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
803 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Ti… in HAL_QSPI_Command() argument
835 __HAL_LOCK(hqspi); in HAL_QSPI_Command()
837 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command()
839 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command()
842 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command()
845 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_Command()
850 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command()
856 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Command()
860 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Command()
863 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
869 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
879 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command()
892 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) in HAL_QSPI_Command_IT() argument
924 __HAL_LOCK(hqspi); in HAL_QSPI_Command_IT()
926 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command_IT()
928 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command_IT()
931 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command_IT()
934 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Command_IT()
941 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Command_IT()
945 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command_IT()
952 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
955 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); in HAL_QSPI_Command_IT()
960 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command_IT()
963 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
969 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
977 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
992 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Transmit() argument
996 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Transmit()
999 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit()
1001 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit()
1003 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit()
1008 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit()
1011 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
1012 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
1013 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit()
1016 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit()
1018 while(hqspi->TxXferCount > 0U) in HAL_QSPI_Transmit()
1021 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
1028 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_Transmit()
1029 hqspi->pTxBuffPtr++; in HAL_QSPI_Transmit()
1030 hqspi->TxXferCount--; in HAL_QSPI_Transmit()
1036 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
1041 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Transmit()
1047 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit()
1051 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit()
1061 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit()
1075 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Receive() argument
1079 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive()
1080 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Receive()
1083 __HAL_LOCK(hqspi); in HAL_QSPI_Receive()
1085 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive()
1087 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive()
1092 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive()
1095 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1096 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1097 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive()
1100 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive()
1103 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive()
1105 while(hqspi->RxXferCount > 0U) in HAL_QSPI_Receive()
1108 …status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Time… in HAL_QSPI_Receive()
1115 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_Receive()
1116 hqspi->pRxBuffPtr++; in HAL_QSPI_Receive()
1117 hqspi->RxXferCount--; in HAL_QSPI_Receive()
1123 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Receive()
1128 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Receive()
1134 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive()
1138 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive()
1148 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive()
1160 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_IT() argument
1165 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_IT()
1167 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_IT()
1169 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_IT()
1174 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_IT()
1177 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1178 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1179 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_IT()
1182 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Transmit_IT()
1185 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_IT()
1188 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1191 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Transmit_IT()
1195 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_IT()
1199 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1207 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1220 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_IT() argument
1223 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_IT()
1226 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_IT()
1228 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_IT()
1230 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_IT()
1235 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_IT()
1238 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1239 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1240 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_IT()
1243 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Receive_IT()
1246 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_IT()
1249 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_IT()
1252 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1255 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Receive_IT()
1259 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_IT()
1263 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1271 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1284 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_DMA() argument
1287 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Transmit_DMA()
1290 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1292 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_DMA()
1295 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_DMA()
1300 hqspi->TxXferCount = data_size; in HAL_QSPI_Transmit_DMA()
1303 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_DMA()
1306 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Transmit_DMA()
1309 hqspi->TxXferSize = hqspi->TxXferCount; in HAL_QSPI_Transmit_DMA()
1310 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_DMA()
1313 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_DMA()
1316 hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt; in HAL_QSPI_Transmit_DMA()
1319 hqspi->hmdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Transmit_DMA()
1322 hqspi->hmdma->XferAbortCallback = NULL; in HAL_QSPI_Transmit_DMA()
1325 …MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABL… in HAL_QSPI_Transmit_DMA()
1328 if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE) in HAL_QSPI_Transmit_DMA()
1330 … MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE); in HAL_QSPI_Transmit_DMA()
1332 else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD) in HAL_QSPI_Transmit_DMA()
1334 …MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWO… in HAL_QSPI_Transmit_DMA()
1336 else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD) in HAL_QSPI_Transmit_DMA()
1338 … MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD); in HAL_QSPI_Transmit_DMA()
1343 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Transmit_DMA()
1348 …if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXfer… in HAL_QSPI_Transmit_DMA()
1351 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1354 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Transmit_DMA()
1361 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Transmit_DMA()
1362 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit_DMA()
1365 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1370 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1374 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1382 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1395 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_DMA() argument
1398 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_DMA()
1399 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Receive_DMA()
1402 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_DMA()
1404 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_DMA()
1407 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_DMA()
1412 hqspi->RxXferCount = data_size; in HAL_QSPI_Receive_DMA()
1414 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_DMA()
1417 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Receive_DMA()
1420 hqspi->RxXferSize = hqspi->RxXferCount; in HAL_QSPI_Receive_DMA()
1421 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_DMA()
1424 hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt; in HAL_QSPI_Receive_DMA()
1427 hqspi->hmdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Receive_DMA()
1430 hqspi->hmdma->XferAbortCallback = NULL; in HAL_QSPI_Receive_DMA()
1433 …MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABL… in HAL_QSPI_Receive_DMA()
1436 if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE) in HAL_QSPI_Receive_DMA()
1438 …MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE); in HAL_QSPI_Receive_DMA()
1440 else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD) in HAL_QSPI_Receive_DMA()
1442 …MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFW… in HAL_QSPI_Receive_DMA()
1444 else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD) in HAL_QSPI_Receive_DMA()
1446 …MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD); in HAL_QSPI_Receive_DMA()
1451 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Receive_DMA()
1458 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_DMA()
1461 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_DMA()
1464 …if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXfer… in HAL_QSPI_Receive_DMA()
1467 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1470 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Receive_DMA()
1473 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Receive_DMA()
1478 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Receive_DMA()
1479 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive_DMA()
1482 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1487 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1491 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1499 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1514 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_Au… in HAL_QSPI_AutoPolling() argument
1550 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling()
1552 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling()
1554 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling()
1557 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling()
1560 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1565 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling()
1568 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling()
1571 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling()
1575 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling()
1580 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling()
1583 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1587 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); in HAL_QSPI_AutoPolling()
1590 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_AutoPolling()
1600 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling()
1614 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI… in HAL_QSPI_AutoPolling_IT() argument
1651 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1653 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling_IT()
1655 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling_IT()
1658 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling_IT()
1661 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_AutoPolling_IT()
1666 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling_IT()
1669 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling_IT()
1672 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling_IT()
1675 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling_IT()
1679 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); in HAL_QSPI_AutoPolling_IT()
1683 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling_IT()
1686 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1689 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_AutoPolling_IT()
1695 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1703 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1718 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_M… in HAL_QSPI_MemoryMapped() argument
1752 __HAL_LOCK(hqspi); in HAL_QSPI_MemoryMapped()
1754 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_MemoryMapped()
1756 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_MemoryMapped()
1759 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; in HAL_QSPI_MemoryMapped()
1762 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_MemoryMapped()
1767 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); in HAL_QSPI_MemoryMapped()
1774 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); in HAL_QSPI_MemoryMapped()
1777 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); in HAL_QSPI_MemoryMapped()
1780 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); in HAL_QSPI_MemoryMapped()
1784 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); in HAL_QSPI_MemoryMapped()
1793 __HAL_UNLOCK(hqspi); in HAL_QSPI_MemoryMapped()
1804 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_ErrorCallback() argument
1807 UNUSED(hqspi); in HAL_QSPI_ErrorCallback()
1819 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_AbortCpltCallback() argument
1822 UNUSED(hqspi); in HAL_QSPI_AbortCpltCallback()
1834 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_CmdCpltCallback() argument
1837 UNUSED(hqspi); in HAL_QSPI_CmdCpltCallback()
1849 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxCpltCallback() argument
1852 UNUSED(hqspi); in HAL_QSPI_RxCpltCallback()
1864 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxCpltCallback() argument
1867 UNUSED(hqspi); in HAL_QSPI_TxCpltCallback()
1879 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxHalfCpltCallback() argument
1882 UNUSED(hqspi); in HAL_QSPI_RxHalfCpltCallback()
1894 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxHalfCpltCallback() argument
1897 UNUSED(hqspi); in HAL_QSPI_TxHalfCpltCallback()
1909 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_FifoThresholdCallback() argument
1912 UNUSED(hqspi); in HAL_QSPI_FifoThresholdCallback()
1924 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_StatusMatchCallback() argument
1927 UNUSED(hqspi); in HAL_QSPI_StatusMatchCallback()
1939 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TimeOutCallback() argument
1942 UNUSED(hqspi); in HAL_QSPI_TimeOutCallback()
1970 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef … in HAL_QSPI_RegisterCallback() argument
1977 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
1982 __HAL_LOCK(hqspi); in HAL_QSPI_RegisterCallback()
1984 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_RegisterCallback()
1989 hqspi->ErrorCallback = pCallback; in HAL_QSPI_RegisterCallback()
1992 hqspi->AbortCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
1995 hqspi->FifoThresholdCallback = pCallback; in HAL_QSPI_RegisterCallback()
1998 hqspi->CmdCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2001 hqspi->RxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2004 hqspi->TxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2007 hqspi->RxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2010 hqspi->TxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2013 hqspi->StatusMatchCallback = pCallback; in HAL_QSPI_RegisterCallback()
2016 hqspi->TimeOutCallback = pCallback; in HAL_QSPI_RegisterCallback()
2019 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2022 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2026 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2032 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_RegisterCallback()
2037 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2040 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2044 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2053 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2059 __HAL_UNLOCK(hqspi); in HAL_QSPI_RegisterCallback()
2083 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDe… in HAL_QSPI_UnRegisterCallback() argument
2088 __HAL_LOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2090 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_UnRegisterCallback()
2095 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_UnRegisterCallback()
2098 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_UnRegisterCallback()
2101 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_UnRegisterCallback()
2104 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_UnRegisterCallback()
2107 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2110 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2113 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2116 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2119 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_UnRegisterCallback()
2122 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_UnRegisterCallback()
2125 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2128 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2132 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2138 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_UnRegisterCallback()
2143 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2146 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2150 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2159 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2165 __HAL_UNLOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2197 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetState() argument
2200 return hqspi->State; in HAL_QSPI_GetState()
2208 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetError() argument
2210 return hqspi->ErrorCode; in HAL_QSPI_GetError()
2218 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort() argument
2224 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort()
2227 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort()
2229 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort()
2232 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort()
2235 status = HAL_MDMA_Abort(hqspi->hmdma); in HAL_QSPI_Abort()
2238 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Abort()
2242 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort()
2245 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort()
2248 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2252 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort()
2255 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2261 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_Abort()
2264 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2270 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2282 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort_IT() argument
2287 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort_IT()
2290 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort_IT()
2293 hqspi->State = HAL_QSPI_STATE_ABORT; in HAL_QSPI_Abort_IT()
2296 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); in HAL_QSPI_Abort_IT()
2298 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort_IT()
2301 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort_IT()
2304 hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_Abort_IT()
2305 if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) in HAL_QSPI_Abort_IT()
2308 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2312 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2314 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2320 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort_IT()
2323 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort_IT()
2326 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in HAL_QSPI_Abort_IT()
2329 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort_IT()
2334 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2346 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) in HAL_QSPI_SetTimeout() argument
2348 hqspi->Timeout = Timeout; in HAL_QSPI_SetTimeout()
2356 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) in HAL_QSPI_SetFifoThreshold() argument
2361 __HAL_LOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2363 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_SetFifoThreshold()
2366 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2369 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_SetFifoThreshold()
2370 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
2378 __HAL_UNLOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2388 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetFifoThreshold() argument
2390 return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); in HAL_QSPI_GetFifoThreshold()
2400 HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) in HAL_QSPI_SetFlashID() argument
2408 __HAL_LOCK(hqspi); in HAL_QSPI_SetFlashID()
2410 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_SetFlashID()
2413 hqspi->Init.FlashID = FlashID; in HAL_QSPI_SetFlashID()
2416 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); in HAL_QSPI_SetFlashID()
2424 __HAL_UNLOCK(hqspi); in HAL_QSPI_SetFlashID()
2449 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent); in QSPI_DMARxCplt() local
2450 hqspi->RxXferCount = 0U; in QSPI_DMARxCplt()
2453 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMARxCplt()
2463 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent); in QSPI_DMATxCplt() local
2464 hqspi->TxXferCount = 0U; in QSPI_DMATxCplt()
2467 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMATxCplt()
2477 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); in QSPI_DMAError() local
2479 hqspi->RxXferCount = 0U; in QSPI_DMAError()
2480 hqspi->TxXferCount = 0U; in QSPI_DMAError()
2481 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in QSPI_DMAError()
2484 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in QSPI_DMAError()
2487 (void)HAL_QSPI_Abort_IT(hqspi); in QSPI_DMAError()
2498 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); in QSPI_DMAAbortCplt() local
2500 hqspi->RxXferCount = 0U; in QSPI_DMAAbortCplt()
2501 hqspi->TxXferCount = 0U; in QSPI_DMAAbortCplt()
2503 if(hqspi->State == HAL_QSPI_STATE_ABORT) in QSPI_DMAAbortCplt()
2507 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in QSPI_DMAAbortCplt()
2510 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMAAbortCplt()
2513 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in QSPI_DMAAbortCplt()
2519 hqspi->State = HAL_QSPI_STATE_READY; in QSPI_DMAAbortCplt()
2523 hqspi->ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2525 HAL_QSPI_ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2539 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, in QSPI_WaitFlagStateUntilTimeout() argument
2543 while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) in QSPI_WaitFlagStateUntilTimeout()
2550 hqspi->State = HAL_QSPI_STATE_ERROR; in QSPI_WaitFlagStateUntilTimeout()
2551 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; in QSPI_WaitFlagStateUntilTimeout()
2572 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod… in QSPI_Config() argument
2579 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); in QSPI_Config()
2587 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2593 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2602 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2609 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2622 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2630 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2637 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2649 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2655 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2664 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2671 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2683 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2691 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2700 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()