Lines Matching refs:hdma
133 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32…
134 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
135 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
136 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
137 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
174 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) in HAL_DMA_Init() argument
181 if (hdma == NULL) in HAL_DMA_Init()
187 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); in HAL_DMA_Init()
188 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); in HAL_DMA_Init()
189 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); in HAL_DMA_Init()
190 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); in HAL_DMA_Init()
191 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); in HAL_DMA_Init()
192 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); in HAL_DMA_Init()
193 assert_param(IS_DMA_MODE(hdma->Init.Mode)); in HAL_DMA_Init()
194 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); in HAL_DMA_Init()
196 if(IS_DMA_INSTANCE(hdma) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_Init()
199 assert_param(IS_DMA_REQUEST(hdma->Init.Request)); in HAL_DMA_Init()
200 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); in HAL_DMA_Init()
203 if (hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) in HAL_DMA_Init()
205 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); in HAL_DMA_Init()
206 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); in HAL_DMA_Init()
207 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); in HAL_DMA_Init()
213 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Init()
216 __HAL_UNLOCK(hdma); in HAL_DMA_Init()
219 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Init()
222 while ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) in HAL_DMA_Init()
228 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_Init()
231 hdma->State = HAL_DMA_STATE_ERROR; in HAL_DMA_Init()
238 registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; in HAL_DMA_Init()
247 registerValue |= hdma->Init.Direction | in HAL_DMA_Init()
248 hdma->Init.PeriphInc | hdma->Init.MemInc | in HAL_DMA_Init()
249 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | in HAL_DMA_Init()
250 hdma->Init.Mode | hdma->Init.Priority; in HAL_DMA_Init()
253 if (hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) in HAL_DMA_Init()
256 registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; in HAL_DMA_Init()
260 ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; in HAL_DMA_Init()
263 registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; in HAL_DMA_Init()
269 registerValue |= hdma->Init.FIFOMode; in HAL_DMA_Init()
272 if (hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) in HAL_DMA_Init()
275 registerValue |= hdma->Init.FIFOThreshold; in HAL_DMA_Init()
279 if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) in HAL_DMA_Init()
281 if (DMA_CheckFifoParam(hdma) != HAL_OK) in HAL_DMA_Init()
284 hdma->ErrorCode = HAL_DMA_ERROR_PARAM; in HAL_DMA_Init()
287 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Init()
295 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; in HAL_DMA_Init()
299 regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_Init()
302 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_Init()
306 hdma->ErrorCode = HAL_DMA_ERROR_PARAM; in HAL_DMA_Init()
307 hdma->State = HAL_DMA_STATE_ERROR; in HAL_DMA_Init()
315 DMA_CalcDMAMUXChannelBaseAndMask(hdma); in HAL_DMA_Init()
317 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) in HAL_DMA_Init()
320 hdma->Init.Request = DMA_REQUEST_MEM2MEM; in HAL_DMA_Init()
325 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); in HAL_DMA_Init()
328 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_Init()
334 …if ((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR… in HAL_DMA_Init()
338 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); in HAL_DMA_Init()
341 hdma->DMAmuxRequestGen->RGCR = 0U; in HAL_DMA_Init()
344 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_Init()
348 hdma->DMAmuxRequestGen = 0U; in HAL_DMA_Init()
349 hdma->DMAmuxRequestGenStatus = 0U; in HAL_DMA_Init()
350 hdma->DMAmuxRequestGenStatusMask = 0U; in HAL_DMA_Init()
354 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Init()
357 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Init()
368 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) in HAL_DMA_DeInit() argument
373 if (hdma == NULL) in HAL_DMA_DeInit()
379 __HAL_DMA_DISABLE(hdma); in HAL_DMA_DeInit()
383 ((DMA_Stream_TypeDef *)hdma->Instance)->CR = 0U; in HAL_DMA_DeInit()
386 ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = 0U; in HAL_DMA_DeInit()
389 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = 0U; in HAL_DMA_DeInit()
392 ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = 0U; in HAL_DMA_DeInit()
395 ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = 0U; in HAL_DMA_DeInit()
398 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U; in HAL_DMA_DeInit()
401 regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_DeInit()
404 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_DeInit()
407 DMA_CalcDMAMUXChannelBaseAndMask(hdma); in HAL_DMA_DeInit()
409 if(hdma->DMAmuxChannel != 0U) in HAL_DMA_DeInit()
412 hdma->DMAmuxChannel->CCR = 0U; in HAL_DMA_DeInit()
415 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_DeInit()
418 …if ((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR… in HAL_DMA_DeInit()
422 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); in HAL_DMA_DeInit()
425 hdma->DMAmuxRequestGen->RGCR = 0U; in HAL_DMA_DeInit()
428 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_DeInit()
431 hdma->DMAmuxRequestGen = 0U; in HAL_DMA_DeInit()
432 hdma->DMAmuxRequestGenStatus = 0U; in HAL_DMA_DeInit()
433 hdma->DMAmuxRequestGenStatusMask = 0U; in HAL_DMA_DeInit()
436 hdma->XferCpltCallback = NULL; in HAL_DMA_DeInit()
437 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_DeInit()
438 hdma->XferM1CpltCallback = NULL; in HAL_DMA_DeInit()
439 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_DeInit()
440 hdma->XferErrorCallback = NULL; in HAL_DMA_DeInit()
441 hdma->XferAbortCallback = NULL; in HAL_DMA_DeInit()
444 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_DeInit()
447 hdma->State = HAL_DMA_STATE_RESET; in HAL_DMA_DeInit()
450 __HAL_UNLOCK(hdma); in HAL_DMA_DeInit()
487 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, … in HAL_DMA_Start() argument
495 if (hdma == NULL) in HAL_DMA_Start()
501 __HAL_LOCK(hdma); in HAL_DMA_Start()
503 if (HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_Start()
506 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start()
509 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start()
512 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Start()
515 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start()
518 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start()
523 hdma->ErrorCode = HAL_DMA_ERROR_BUSY; in HAL_DMA_Start()
526 __HAL_UNLOCK(hdma); in HAL_DMA_Start()
543 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres… in HAL_DMA_Start_IT() argument
551 if (hdma == NULL) in HAL_DMA_Start_IT()
557 __HAL_LOCK(hdma); in HAL_DMA_Start_IT()
559 if (HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_Start_IT()
562 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start_IT()
565 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start_IT()
568 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Start_IT()
571 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start_IT()
574 …MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_I… in HAL_DMA_Start_IT()
575 if (hdma->XferHalfCpltCallback != NULL) in HAL_DMA_Start_IT()
578 ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; in HAL_DMA_Start_IT()
582 if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) in HAL_DMA_Start_IT()
585 hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; in HAL_DMA_Start_IT()
588 if(hdma->DMAmuxRequestGen != 0U) in HAL_DMA_Start_IT()
592 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; in HAL_DMA_Start_IT()
597 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start_IT()
602 hdma->ErrorCode = HAL_DMA_ERROR_BUSY; in HAL_DMA_Start_IT()
605 __HAL_UNLOCK(hdma); in HAL_DMA_Start_IT()
626 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort() argument
635 if (hdma == NULL) in HAL_DMA_Abort()
641 if (hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort()
643 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort()
646 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
653 … ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); in HAL_DMA_Abort()
654 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); in HAL_DMA_Abort()
656 enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); in HAL_DMA_Abort()
659 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMA_Abort()
662 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort()
671 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_Abort()
674 hdma->State = HAL_DMA_STATE_ERROR; in HAL_DMA_Abort()
677 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
682 regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_Abort()
683 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_Abort()
686 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_Abort()
688 if(hdma->DMAmuxRequestGen != 0U) in HAL_DMA_Abort()
692 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; in HAL_DMA_Abort()
695 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_Abort()
699 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Abort()
701 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
712 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort_IT() argument
715 if (hdma == NULL) in HAL_DMA_Abort_IT()
720 if (hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort_IT()
722 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort_IT()
728 hdma->State = HAL_DMA_STATE_ABORT; in HAL_DMA_Abort_IT()
731 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort_IT()
748 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com… in HAL_DMA_PollForTransfer() argument
760 if (hdma == NULL) in HAL_DMA_PollForTransfer()
765 if (HAL_DMA_STATE_BUSY != hdma->State) in HAL_DMA_PollForTransfer()
768 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_PollForTransfer()
769 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
774 if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U) in HAL_DMA_PollForTransfer()
776 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; in HAL_DMA_PollForTransfer()
784 cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
789 cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
792 isr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); in HAL_DMA_PollForTransfer()
793 ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); in HAL_DMA_PollForTransfer()
797 if(IS_DMA_INSTANCE(hdma) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_PollForTransfer()
799 if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_PollForTransfer()
802 hdma->ErrorCode |= HAL_DMA_ERROR_FE; in HAL_DMA_PollForTransfer()
805 (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
808 if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_PollForTransfer()
811 hdma->ErrorCode |= HAL_DMA_ERROR_DME; in HAL_DMA_PollForTransfer()
814 (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
817 if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_PollForTransfer()
820 hdma->ErrorCode |= HAL_DMA_ERROR_TE; in HAL_DMA_PollForTransfer()
823 (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
826 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
829 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
843 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_PollForTransfer()
847 (void) HAL_DMA_Abort(hdma); in HAL_DMA_PollForTransfer()
861 if(hdma->DMAmuxRequestGen != 0U) in HAL_DMA_PollForTransfer()
864 if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) in HAL_DMA_PollForTransfer()
867 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_PollForTransfer()
870 hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; in HAL_DMA_PollForTransfer()
875 if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) in HAL_DMA_PollForTransfer()
878 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_PollForTransfer()
881 hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; in HAL_DMA_PollForTransfer()
890 if(IS_DMA_INSTANCE(hdma) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_PollForTransfer()
892 (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
894 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
896 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
901 if(IS_DMA_INSTANCE(hdma) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_PollForTransfer()
903 (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
916 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) in HAL_DMA_IRQHandler() argument
923 DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_IRQHandler()
927 if(IS_DMA_INSTANCE(hdma) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_IRQHandler()
930 if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_IRQHandler()
932 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) in HAL_DMA_IRQHandler()
935 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); in HAL_DMA_IRQHandler()
938 regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
941 hdma->ErrorCode |= HAL_DMA_ERROR_TE; in HAL_DMA_IRQHandler()
945 if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_IRQHandler()
947 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) in HAL_DMA_IRQHandler()
950 regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
953 hdma->ErrorCode |= HAL_DMA_ERROR_FE; in HAL_DMA_IRQHandler()
957 if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_IRQHandler()
959 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) in HAL_DMA_IRQHandler()
962 regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
965 hdma->ErrorCode |= HAL_DMA_ERROR_DME; in HAL_DMA_IRQHandler()
969 if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_IRQHandler()
971 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) in HAL_DMA_IRQHandler()
974 regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
977 if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) in HAL_DMA_IRQHandler()
980 if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) in HAL_DMA_IRQHandler()
982 if (hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
985 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
991 if (hdma->XferM1HalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
994 hdma->XferM1HalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
1001 if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) in HAL_DMA_IRQHandler()
1004 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); in HAL_DMA_IRQHandler()
1007 if (hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
1010 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
1016 if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_IRQHandler()
1018 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) in HAL_DMA_IRQHandler()
1021 regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1023 if (HAL_DMA_STATE_ABORT == hdma->State) in HAL_DMA_IRQHandler()
1026 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); in HAL_DMA_IRQHandler()
1027 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); in HAL_DMA_IRQHandler()
1029 if ((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) in HAL_DMA_IRQHandler()
1031 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); in HAL_DMA_IRQHandler()
1035 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1038 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
1041 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
1043 if (hdma->XferAbortCallback != NULL) in HAL_DMA_IRQHandler()
1045 hdma->XferAbortCallback(hdma); in HAL_DMA_IRQHandler()
1050 if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) in HAL_DMA_IRQHandler()
1053 if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) in HAL_DMA_IRQHandler()
1055 if (hdma->XferM1CpltCallback != NULL) in HAL_DMA_IRQHandler()
1058 hdma->XferM1CpltCallback(hdma); in HAL_DMA_IRQHandler()
1064 if (hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
1067 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
1074 if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) in HAL_DMA_IRQHandler()
1077 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); in HAL_DMA_IRQHandler()
1080 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
1082 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
1085 if (hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
1088 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
1095 if (hdma->ErrorCode != HAL_DMA_ERROR_NONE) in HAL_DMA_IRQHandler()
1097 if ((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) in HAL_DMA_IRQHandler()
1099 hdma->State = HAL_DMA_STATE_ABORT; in HAL_DMA_IRQHandler()
1102 __HAL_DMA_DISABLE(hdma); in HAL_DMA_IRQHandler()
1111 while ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); in HAL_DMA_IRQHandler()
1113 if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) in HAL_DMA_IRQHandler()
1116 hdma->State = HAL_DMA_STATE_ERROR; in HAL_DMA_IRQHandler()
1121 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
1124 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
1127 if (hdma->XferErrorCallback != NULL) in HAL_DMA_IRQHandler()
1130 hdma->XferErrorCallback(hdma); in HAL_DMA_IRQHandler()
1150 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb… in HAL_DMA_RegisterCallback() argument
1156 if (hdma == NULL) in HAL_DMA_RegisterCallback()
1162 __HAL_LOCK(hdma); in HAL_DMA_RegisterCallback()
1164 if (HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_RegisterCallback()
1169 hdma->XferCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
1173 hdma->XferHalfCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
1177 hdma->XferM1CpltCallback = pCallback; in HAL_DMA_RegisterCallback()
1181 hdma->XferM1HalfCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
1185 hdma->XferErrorCallback = pCallback; in HAL_DMA_RegisterCallback()
1189 hdma->XferAbortCallback = pCallback; in HAL_DMA_RegisterCallback()
1204 __HAL_UNLOCK(hdma); in HAL_DMA_RegisterCallback()
1217 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal… in HAL_DMA_UnRegisterCallback() argument
1222 if (hdma == NULL) in HAL_DMA_UnRegisterCallback()
1228 __HAL_LOCK(hdma); in HAL_DMA_UnRegisterCallback()
1230 if (HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_UnRegisterCallback()
1235 hdma->XferCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1239 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1243 hdma->XferM1CpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1247 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1251 hdma->XferErrorCallback = NULL; in HAL_DMA_UnRegisterCallback()
1255 hdma->XferAbortCallback = NULL; in HAL_DMA_UnRegisterCallback()
1259 hdma->XferCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1260 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1261 hdma->XferM1CpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1262 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1263 hdma->XferErrorCallback = NULL; in HAL_DMA_UnRegisterCallback()
1264 hdma->XferAbortCallback = NULL; in HAL_DMA_UnRegisterCallback()
1278 __HAL_UNLOCK(hdma); in HAL_DMA_UnRegisterCallback()
1308 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) in HAL_DMA_GetState() argument
1310 return hdma->State; in HAL_DMA_GetState()
1319 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) in HAL_DMA_GetError() argument
1321 return hdma->ErrorCode; in HAL_DMA_GetError()
1345 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32… in DMA_SetConfig() argument
1348 DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; in DMA_SetConfig()
1351 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in DMA_SetConfig()
1353 if(hdma->DMAmuxRequestGen != 0U) in DMA_SetConfig()
1356 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in DMA_SetConfig()
1359 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in DMA_SetConfig()
1362 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); in DMA_SetConfig()
1365 ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; in DMA_SetConfig()
1368 if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) in DMA_SetConfig()
1371 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; in DMA_SetConfig()
1374 ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; in DMA_SetConfig()
1380 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; in DMA_SetConfig()
1383 ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; in DMA_SetConfig()
1393 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) in DMA_CalcBaseAndBitshift() argument
1395 uint32_t stream_number = (((uint32_t)((uint32_t *)hdma->Instance) & 0xFFU) - 16U) / 24U; in DMA_CalcBaseAndBitshift()
1399 hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; in DMA_CalcBaseAndBitshift()
1404 hdma->StreamBaseAddress = (((uint32_t)((uint32_t *)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); in DMA_CalcBaseAndBitshift()
1409 hdma->StreamBaseAddress = ((uint32_t)((uint32_t *)hdma->Instance) & (uint32_t)(~0x3FFU)); in DMA_CalcBaseAndBitshift()
1412 return hdma->StreamBaseAddress; in DMA_CalcBaseAndBitshift()
1421 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) in DMA_CheckFifoParam() argument
1426 if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) in DMA_CheckFifoParam()
1428 switch (hdma->Init.FIFOThreshold) in DMA_CheckFifoParam()
1433 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1440 if (hdma->Init.MemBurst == DMA_MBURST_INC16) in DMA_CheckFifoParam()
1455 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) in DMA_CheckFifoParam()
1457 switch (hdma->Init.FIFOThreshold) in DMA_CheckFifoParam()
1465 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1472 if (hdma->Init.MemBurst == DMA_MBURST_INC16) in DMA_CheckFifoParam()
1486 switch (hdma->Init.FIFOThreshold) in DMA_CheckFifoParam()
1495 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1515 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) in DMA_CalcDMAMUXChannelBaseAndMask() argument
1518 uint32_t stream_baseaddress = (uint32_t)((uint32_t *)hdma->Instance); in DMA_CalcDMAMUXChannelBaseAndMask()
1520 stream_number = (((uint32_t)((uint32_t *)hdma->Instance) & 0xFFU) - 16U) / 24U; in DMA_CalcDMAMUXChannelBaseAndMask()
1528 …hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream… in DMA_CalcDMAMUXChannelBaseAndMask()
1529 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; in DMA_CalcDMAMUXChannelBaseAndMask()
1530 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); in DMA_CalcDMAMUXChannelBaseAndMask()
1540 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) in DMA_CalcDMAMUXRequestGenBaseAndMask() argument
1542 uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; in DMA_CalcDMAMUXRequestGenBaseAndMask()
1547 …hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenera… in DMA_CalcDMAMUXRequestGenBaseAndMask()
1548 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; in DMA_CalcDMAMUXRequestGenBaseAndMask()
1549 hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); in DMA_CalcDMAMUXRequestGenBaseAndMask()