302      regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_Init()
404   regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_DeInit()
683     regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_Abort()
784       cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_PollForTransfer()
789       cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_PollForTransfer()
799       if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)  in HAL_DMA_PollForTransfer()
805         (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_PollForTransfer()
808       if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)  in HAL_DMA_PollForTransfer()
814         (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_PollForTransfer()
817       if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)  in HAL_DMA_PollForTransfer()
823         (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_PollForTransfer()
892       (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_PollForTransfer()
903     (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_PollForTransfer()
930     if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)  in HAL_DMA_IRQHandler()
938         regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_IRQHandler()
945     if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)  in HAL_DMA_IRQHandler()
950         regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_IRQHandler()
957     if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)  in HAL_DMA_IRQHandler()
962         regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_IRQHandler()
969     if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)  in HAL_DMA_IRQHandler()
974         regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_IRQHandler()
1016     if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)  in HAL_DMA_IRQHandler()
1021         regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_IRQHandler()
1035           regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);  in HAL_DMA_IRQHandler()
1359     regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);  in DMA_SetConfig()
1399   hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];  in DMA_CalcBaseAndBitshift()