Lines Matching refs:TIMx
1430 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) in LL_TIM_EnableCounter() argument
1432 SET_BIT(TIMx->CR1, TIM_CR1_CEN); in LL_TIM_EnableCounter()
1441 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) in LL_TIM_DisableCounter() argument
1443 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); in LL_TIM_DisableCounter()
1452 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledCounter() argument
1454 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); in LL_TIM_IsEnabledCounter()
1463 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) in LL_TIM_EnableUpdateEvent() argument
1465 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); in LL_TIM_EnableUpdateEvent()
1474 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) in LL_TIM_DisableUpdateEvent() argument
1476 SET_BIT(TIMx->CR1, TIM_CR1_UDIS); in LL_TIM_DisableUpdateEvent()
1485 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledUpdateEvent() argument
1487 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); in LL_TIM_IsEnabledUpdateEvent()
1506 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) in LL_TIM_SetUpdateSource() argument
1508 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); in LL_TIM_SetUpdateSource()
1519 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) in LL_TIM_GetUpdateSource() argument
1521 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); in LL_TIM_GetUpdateSource()
1533 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) in LL_TIM_SetOnePulseMode() argument
1535 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); in LL_TIM_SetOnePulseMode()
1546 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) in LL_TIM_GetOnePulseMode() argument
1548 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); in LL_TIM_GetOnePulseMode()
1570 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) in LL_TIM_SetCounterMode() argument
1572 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); in LL_TIM_SetCounterMode()
1590 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) in LL_TIM_GetCounterMode() argument
1592 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); in LL_TIM_GetCounterMode()
1601 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) in LL_TIM_EnableARRPreload() argument
1603 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); in LL_TIM_EnableARRPreload()
1612 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) in LL_TIM_DisableARRPreload() argument
1614 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); in LL_TIM_DisableARRPreload()
1623 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledARRPreload() argument
1625 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledARRPreload()
1641 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) in LL_TIM_SetClockDivision() argument
1643 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); in LL_TIM_SetClockDivision()
1658 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) in LL_TIM_GetClockDivision() argument
1660 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); in LL_TIM_GetClockDivision()
1672 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) in LL_TIM_SetCounter() argument
1674 WRITE_REG(TIMx->CNT, Counter); in LL_TIM_SetCounter()
1685 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) in LL_TIM_GetCounter() argument
1687 return (uint32_t)(READ_REG(TIMx->CNT)); in LL_TIM_GetCounter()
1698 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) in LL_TIM_GetDirection() argument
1700 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); in LL_TIM_GetDirection()
1714 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) in LL_TIM_SetPrescaler() argument
1716 WRITE_REG(TIMx->PSC, Prescaler); in LL_TIM_SetPrescaler()
1725 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) in LL_TIM_GetPrescaler() argument
1727 return (uint32_t)(READ_REG(TIMx->PSC)); in LL_TIM_GetPrescaler()
1741 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) in LL_TIM_SetAutoReload() argument
1743 WRITE_REG(TIMx->ARR, AutoReload); in LL_TIM_SetAutoReload()
1754 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) in LL_TIM_GetAutoReload() argument
1756 return (uint32_t)(READ_REG(TIMx->ARR)); in LL_TIM_GetAutoReload()
1769 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) in LL_TIM_SetRepetitionCounter() argument
1771 WRITE_REG(TIMx->RCR, RepetitionCounter); in LL_TIM_SetRepetitionCounter()
1782 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) in LL_TIM_GetRepetitionCounter() argument
1784 return (uint32_t)(READ_REG(TIMx->RCR)); in LL_TIM_GetRepetitionCounter()
1794 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) in LL_TIM_EnableUIFRemap() argument
1796 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); in LL_TIM_EnableUIFRemap()
1805 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) in LL_TIM_DisableUIFRemap() argument
1807 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); in LL_TIM_DisableUIFRemap()
1828 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) in LL_TIM_CC_EnablePreload() argument
1830 SET_BIT(TIMx->CR2, TIM_CR2_CCPC); in LL_TIM_CC_EnablePreload()
1841 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) in LL_TIM_CC_DisablePreload() argument
1843 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); in LL_TIM_CC_DisablePreload()
1857 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) in LL_TIM_CC_SetUpdate() argument
1859 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); in LL_TIM_CC_SetUpdate()
1871 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) in LL_TIM_CC_SetDMAReqTrigger() argument
1873 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); in LL_TIM_CC_SetDMAReqTrigger()
1884 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) in LL_TIM_CC_GetDMAReqTrigger() argument
1886 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); in LL_TIM_CC_GetDMAReqTrigger()
1903 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) in LL_TIM_CC_SetLockLevel() argument
1905 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); in LL_TIM_CC_SetLockLevel()
1932 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) in LL_TIM_CC_EnableChannel() argument
1934 SET_BIT(TIMx->CCER, Channels); in LL_TIM_CC_EnableChannel()
1961 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) in LL_TIM_CC_DisableChannel() argument
1963 CLEAR_BIT(TIMx->CCER, Channels); in LL_TIM_CC_DisableChannel()
1990 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) in LL_TIM_CC_IsEnabledChannel() argument
1992 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); in LL_TIM_CC_IsEnabledChannel()
2035 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura… in LL_TIM_OC_ConfigOutput() argument
2038 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_OC_ConfigOutput()
2040 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_OC_ConfigOutput()
2042 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), in LL_TIM_OC_ConfigOutput()
2080 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) in LL_TIM_OC_SetMode() argument
2083 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_OC_SetMode()
2119 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_GetMode() argument
2122 …register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSE… in LL_TIM_OC_GetMode()
2153 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) in LL_TIM_OC_SetPolarity() argument
2156 …MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iC… in LL_TIM_OC_SetPolarity()
2185 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_GetPolarity() argument
2188 …return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChann… in LL_TIM_OC_GetPolarity()
2222 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) in LL_TIM_OC_SetIdleState() argument
2225 …MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iCh… in LL_TIM_OC_SetIdleState()
2254 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_GetIdleState() argument
2257 …return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel… in LL_TIM_OC_GetIdleState()
2279 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_EnableFast() argument
2282 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_OC_EnableFast()
2305 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_DisableFast() argument
2308 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_OC_DisableFast()
2331 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_IsEnabledFast() argument
2334 …register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSE… in LL_TIM_OC_IsEnabledFast()
2357 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_EnablePreload() argument
2360 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_OC_EnablePreload()
2382 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_DisablePreload() argument
2385 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_OC_DisablePreload()
2407 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_IsEnabledPreload() argument
2410 …register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSE… in LL_TIM_OC_IsEnabledPreload()
2436 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_EnableClear() argument
2439 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_OC_EnableClear()
2463 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_DisableClear() argument
2466 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_OC_DisableClear()
2492 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_IsEnabledClear() argument
2495 …register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSE… in LL_TIM_OC_IsEnabledClear()
2510 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) in LL_TIM_OC_SetDeadTime() argument
2512 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); in LL_TIM_OC_SetDeadTime()
2527 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) in LL_TIM_OC_SetCompareCH1() argument
2529 WRITE_REG(TIMx->CCR1, CompareValue); in LL_TIM_OC_SetCompareCH1()
2544 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) in LL_TIM_OC_SetCompareCH2() argument
2546 WRITE_REG(TIMx->CCR2, CompareValue); in LL_TIM_OC_SetCompareCH2()
2561 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) in LL_TIM_OC_SetCompareCH3() argument
2563 WRITE_REG(TIMx->CCR3, CompareValue); in LL_TIM_OC_SetCompareCH3()
2578 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) in LL_TIM_OC_SetCompareCH4() argument
2580 WRITE_REG(TIMx->CCR4, CompareValue); in LL_TIM_OC_SetCompareCH4()
2592 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) in LL_TIM_OC_SetCompareCH5() argument
2594 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); in LL_TIM_OC_SetCompareCH5()
2606 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) in LL_TIM_OC_SetCompareCH6() argument
2608 WRITE_REG(TIMx->CCR6, CompareValue); in LL_TIM_OC_SetCompareCH6()
2622 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) in LL_TIM_OC_GetCompareCH1() argument
2624 return (uint32_t)(READ_REG(TIMx->CCR1)); in LL_TIM_OC_GetCompareCH1()
2638 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) in LL_TIM_OC_GetCompareCH2() argument
2640 return (uint32_t)(READ_REG(TIMx->CCR2)); in LL_TIM_OC_GetCompareCH2()
2654 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) in LL_TIM_OC_GetCompareCH3() argument
2656 return (uint32_t)(READ_REG(TIMx->CCR3)); in LL_TIM_OC_GetCompareCH3()
2670 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) in LL_TIM_OC_GetCompareCH4() argument
2672 return (uint32_t)(READ_REG(TIMx->CCR4)); in LL_TIM_OC_GetCompareCH4()
2683 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) in LL_TIM_OC_GetCompareCH5() argument
2685 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); in LL_TIM_OC_GetCompareCH5()
2696 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) in LL_TIM_OC_GetCompareCH6() argument
2698 return (uint32_t)(READ_REG(TIMx->CCR6)); in LL_TIM_OC_GetCompareCH6()
2716 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) in LL_TIM_SetCH5CombinedChannels() argument
2718 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); in LL_TIM_SetCH5CombinedChannels()
2763 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2766 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_IC_Config()
2769 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config()
2791 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv… in LL_TIM_IC_SetActiveInput() argument
2794 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_IC_SetActiveInput()
2815 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_IC_GetActiveInput() argument
2818 …register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSE… in LL_TIM_IC_GetActiveInput()
2841 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal… in LL_TIM_IC_SetPrescaler() argument
2844 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_IC_SetPrescaler()
2866 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_IC_GetPrescaler() argument
2869 …register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSE… in LL_TIM_IC_GetPrescaler()
2904 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) in LL_TIM_IC_SetFilter() argument
2907 …register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_… in LL_TIM_IC_SetFilter()
2941 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_IC_GetFilter() argument
2944 …register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSE… in LL_TIM_IC_GetFilter()
2970 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) in LL_TIM_IC_SetPolarity() argument
2973 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity()
2998 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_IC_GetPolarity() argument
3001 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
3013 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) in LL_TIM_IC_EnableXORCombination() argument
3015 SET_BIT(TIMx->CR2, TIM_CR2_TI1S); in LL_TIM_IC_EnableXORCombination()
3026 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) in LL_TIM_IC_DisableXORCombination() argument
3028 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); in LL_TIM_IC_DisableXORCombination()
3039 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) in LL_TIM_IC_IsEnabledXORCombination() argument
3041 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); in LL_TIM_IC_IsEnabledXORCombination()
3055 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) in LL_TIM_IC_GetCaptureCH1() argument
3057 return (uint32_t)(READ_REG(TIMx->CCR1)); in LL_TIM_IC_GetCaptureCH1()
3071 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) in LL_TIM_IC_GetCaptureCH2() argument
3073 return (uint32_t)(READ_REG(TIMx->CCR2)); in LL_TIM_IC_GetCaptureCH2()
3087 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) in LL_TIM_IC_GetCaptureCH3() argument
3089 return (uint32_t)(READ_REG(TIMx->CCR3)); in LL_TIM_IC_GetCaptureCH3()
3103 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) in LL_TIM_IC_GetCaptureCH4() argument
3105 return (uint32_t)(READ_REG(TIMx->CCR4)); in LL_TIM_IC_GetCaptureCH4()
3124 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) in LL_TIM_EnableExternalClock() argument
3126 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); in LL_TIM_EnableExternalClock()
3137 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) in LL_TIM_DisableExternalClock() argument
3139 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); in LL_TIM_DisableExternalClock()
3150 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledExternalClock() argument
3152 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); in LL_TIM_IsEnabledExternalClock()
3174 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) in LL_TIM_SetClockSource() argument
3176 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); in LL_TIM_SetClockSource()
3191 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) in LL_TIM_SetEncoderMode() argument
3193 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); in LL_TIM_SetEncoderMode()
3220 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) in LL_TIM_SetTriggerOutput() argument
3222 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); in LL_TIM_SetTriggerOutput()
3250 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) in LL_TIM_SetTriggerOutput2() argument
3252 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); in LL_TIM_SetTriggerOutput2()
3269 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) in LL_TIM_SetSlaveMode() argument
3271 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); in LL_TIM_SetSlaveMode()
3291 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) in LL_TIM_SetTriggerInput() argument
3293 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); in LL_TIM_SetTriggerInput()
3304 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) in LL_TIM_EnableMasterSlaveMode() argument
3306 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); in LL_TIM_EnableMasterSlaveMode()
3317 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) in LL_TIM_DisableMasterSlaveMode() argument
3319 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); in LL_TIM_DisableMasterSlaveMode()
3330 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledMasterSlaveMode() argument
3332 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); in LL_TIM_IsEnabledMasterSlaveMode()
3370 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale… in LL_TIM_ConfigETR() argument
3373 …MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | E… in LL_TIM_ConfigETR()
3412 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) in LL_TIM_SetETRSource() argument
3415 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); in LL_TIM_SetETRSource()
3433 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) in LL_TIM_EnableBRK() argument
3435 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); in LL_TIM_EnableBRK()
3446 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) in LL_TIM_DisableBRK() argument
3448 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); in LL_TIM_DisableBRK()
3493 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilt… in LL_TIM_ConfigBRK() argument
3496 …MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter |… in LL_TIM_ConfigBRK()
3509 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) in LL_TIM_DisarmBRK() argument
3511 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); in LL_TIM_DisarmBRK()
3521 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) in LL_TIM_ReArmBRK() argument
3523 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); in LL_TIM_ReArmBRK()
3534 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) in LL_TIM_EnableBRK2() argument
3536 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); in LL_TIM_EnableBRK2()
3547 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) in LL_TIM_DisableBRK2() argument
3549 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); in LL_TIM_DisableBRK2()
3594 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2F… in LL_TIM_ConfigBRK2() argument
3597 …MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Fil… in LL_TIM_ConfigBRK2()
3610 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) in LL_TIM_DisarmBRK2() argument
3612 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); in LL_TIM_DisarmBRK2()
3622 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) in LL_TIM_ReArmBRK2() argument
3624 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); in LL_TIM_ReArmBRK2()
3642 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat… in LL_TIM_SetOffStates() argument
3644 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); in LL_TIM_SetOffStates()
3655 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) in LL_TIM_EnableAutomaticOutput() argument
3657 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); in LL_TIM_EnableAutomaticOutput()
3668 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) in LL_TIM_DisableAutomaticOutput() argument
3670 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); in LL_TIM_DisableAutomaticOutput()
3681 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledAutomaticOutput() argument
3683 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAutomaticOutput()
3696 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) in LL_TIM_EnableAllOutputs() argument
3698 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); in LL_TIM_EnableAllOutputs()
3711 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) in LL_TIM_DisableAllOutputs() argument
3713 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); in LL_TIM_DisableAllOutputs()
3724 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledAllOutputs() argument
3726 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAllOutputs()
3746 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t… in LL_TIM_EnableBreakInputSource() argument
3748 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); in LL_TIM_EnableBreakInputSource()
3769 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_… in LL_TIM_DisableBreakInputSource() argument
3771 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); in LL_TIM_DisableBreakInputSource()
3793 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uin… in LL_TIM_SetBreakInputSourcePolarity() argument
3796 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); in LL_TIM_SetBreakInputSourcePolarity()
3859 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_… in LL_TIM_ConfigDMABurst() argument
3861 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); in LL_TIM_ConfigDMABurst()
4015 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) in LL_TIM_SetRemap() argument
4017 …MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL… in LL_TIM_SetRemap()
4033 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_UPDATE() argument
4035 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); in LL_TIM_ClearFlag_UPDATE()
4044 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_UPDATE() argument
4046 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_UPDATE()
4055 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC1() argument
4057 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); in LL_TIM_ClearFlag_CC1()
4066 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC1() argument
4068 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC1()
4077 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC2() argument
4079 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); in LL_TIM_ClearFlag_CC2()
4088 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC2() argument
4090 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC2()
4099 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC3() argument
4101 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); in LL_TIM_ClearFlag_CC3()
4110 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC3() argument
4112 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC3()
4121 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC4() argument
4123 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); in LL_TIM_ClearFlag_CC4()
4132 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC4() argument
4134 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC4()
4143 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC5() argument
4145 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); in LL_TIM_ClearFlag_CC5()
4154 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC5() argument
4156 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC5()
4165 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC6() argument
4167 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); in LL_TIM_ClearFlag_CC6()
4176 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC6() argument
4178 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC6()
4187 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_COM() argument
4189 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); in LL_TIM_ClearFlag_COM()
4198 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_COM() argument
4200 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_COM()
4209 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_TRIG() argument
4211 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); in LL_TIM_ClearFlag_TRIG()
4220 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_TRIG() argument
4222 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_TRIG()
4231 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_BRK() argument
4233 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); in LL_TIM_ClearFlag_BRK()
4242 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_BRK() argument
4244 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_BRK()
4253 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_BRK2() argument
4255 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); in LL_TIM_ClearFlag_BRK2()
4264 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_BRK2() argument
4266 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_BRK2()
4275 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC1OVR() argument
4277 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); in LL_TIM_ClearFlag_CC1OVR()
4286 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC1OVR() argument
4288 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC1OVR()
4297 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC2OVR() argument
4299 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); in LL_TIM_ClearFlag_CC2OVR()
4308 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC2OVR() argument
4310 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC2OVR()
4319 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC3OVR() argument
4321 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); in LL_TIM_ClearFlag_CC3OVR()
4330 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC3OVR() argument
4332 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC3OVR()
4341 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC4OVR() argument
4343 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); in LL_TIM_ClearFlag_CC4OVR()
4352 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC4OVR() argument
4354 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC4OVR()
4363 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_SYSBRK() argument
4365 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); in LL_TIM_ClearFlag_SYSBRK()
4374 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_SYSBRK() argument
4376 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_SYSBRK()
4392 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_UPDATE() argument
4394 SET_BIT(TIMx->DIER, TIM_DIER_UIE); in LL_TIM_EnableIT_UPDATE()
4403 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_UPDATE() argument
4405 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); in LL_TIM_DisableIT_UPDATE()
4414 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_UPDATE() argument
4416 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_UPDATE()
4425 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_CC1() argument
4427 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); in LL_TIM_EnableIT_CC1()
4436 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_CC1() argument
4438 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); in LL_TIM_DisableIT_CC1()
4447 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_CC1() argument
4449 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_CC1()
4458 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_CC2() argument
4460 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); in LL_TIM_EnableIT_CC2()
4469 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_CC2() argument
4471 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); in LL_TIM_DisableIT_CC2()
4480 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_CC2() argument
4482 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_CC2()
4491 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_CC3() argument
4493 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); in LL_TIM_EnableIT_CC3()
4502 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_CC3() argument
4504 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); in LL_TIM_DisableIT_CC3()
4513 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_CC3() argument
4515 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_CC3()
4524 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_CC4() argument
4526 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); in LL_TIM_EnableIT_CC4()
4535 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_CC4() argument
4537 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); in LL_TIM_DisableIT_CC4()
4546 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_CC4() argument
4548 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_CC4()
4557 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_COM() argument
4559 SET_BIT(TIMx->DIER, TIM_DIER_COMIE); in LL_TIM_EnableIT_COM()
4568 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_COM() argument
4570 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); in LL_TIM_DisableIT_COM()
4579 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_COM() argument
4581 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_COM()
4590 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_TRIG() argument
4592 SET_BIT(TIMx->DIER, TIM_DIER_TIE); in LL_TIM_EnableIT_TRIG()
4601 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_TRIG() argument
4603 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); in LL_TIM_DisableIT_TRIG()
4612 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_TRIG() argument
4614 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_TRIG()
4623 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_BRK() argument
4625 SET_BIT(TIMx->DIER, TIM_DIER_BIE); in LL_TIM_EnableIT_BRK()
4634 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_BRK() argument
4636 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); in LL_TIM_DisableIT_BRK()
4645 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_BRK() argument
4647 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_BRK()
4663 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_UPDATE() argument
4665 SET_BIT(TIMx->DIER, TIM_DIER_UDE); in LL_TIM_EnableDMAReq_UPDATE()
4674 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_UPDATE() argument
4676 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); in LL_TIM_DisableDMAReq_UPDATE()
4685 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_UPDATE() argument
4687 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_UPDATE()
4696 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_CC1() argument
4698 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); in LL_TIM_EnableDMAReq_CC1()
4707 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_CC1() argument
4709 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); in LL_TIM_DisableDMAReq_CC1()
4718 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_CC1() argument
4720 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_CC1()
4729 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_CC2() argument
4731 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); in LL_TIM_EnableDMAReq_CC2()
4740 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_CC2() argument
4742 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); in LL_TIM_DisableDMAReq_CC2()
4751 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_CC2() argument
4753 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_CC2()
4762 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_CC3() argument
4764 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); in LL_TIM_EnableDMAReq_CC3()
4773 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_CC3() argument
4775 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); in LL_TIM_DisableDMAReq_CC3()
4784 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_CC3() argument
4786 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_CC3()
4795 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_CC4() argument
4797 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); in LL_TIM_EnableDMAReq_CC4()
4806 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_CC4() argument
4808 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); in LL_TIM_DisableDMAReq_CC4()
4817 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_CC4() argument
4819 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_CC4()
4828 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_COM() argument
4830 SET_BIT(TIMx->DIER, TIM_DIER_COMDE); in LL_TIM_EnableDMAReq_COM()
4839 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_COM() argument
4841 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); in LL_TIM_DisableDMAReq_COM()
4850 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_COM() argument
4852 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_COM()
4861 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_TRIG() argument
4863 SET_BIT(TIMx->DIER, TIM_DIER_TDE); in LL_TIM_EnableDMAReq_TRIG()
4872 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_TRIG() argument
4874 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); in LL_TIM_DisableDMAReq_TRIG()
4883 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_TRIG() argument
4885 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_TRIG()
4901 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_UPDATE() argument
4903 SET_BIT(TIMx->EGR, TIM_EGR_UG); in LL_TIM_GenerateEvent_UPDATE()
4912 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_CC1() argument
4914 SET_BIT(TIMx->EGR, TIM_EGR_CC1G); in LL_TIM_GenerateEvent_CC1()
4923 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_CC2() argument
4925 SET_BIT(TIMx->EGR, TIM_EGR_CC2G); in LL_TIM_GenerateEvent_CC2()
4934 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_CC3() argument
4936 SET_BIT(TIMx->EGR, TIM_EGR_CC3G); in LL_TIM_GenerateEvent_CC3()
4945 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_CC4() argument
4947 SET_BIT(TIMx->EGR, TIM_EGR_CC4G); in LL_TIM_GenerateEvent_CC4()
4956 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_COM() argument
4958 SET_BIT(TIMx->EGR, TIM_EGR_COMG); in LL_TIM_GenerateEvent_COM()
4967 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_TRIG() argument
4969 SET_BIT(TIMx->EGR, TIM_EGR_TG); in LL_TIM_GenerateEvent_TRIG()
4978 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_BRK() argument
4980 SET_BIT(TIMx->EGR, TIM_EGR_BG); in LL_TIM_GenerateEvent_BRK()
4989 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_BRK2() argument
4991 SET_BIT(TIMx->EGR, TIM_EGR_B2G); in LL_TIM_GenerateEvent_BRK2()
5003 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
5005 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
5007 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitS…
5009 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitS…
5011 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruc…
5013 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensor…
5015 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);