334 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)  in LL_AHB2_GRP1_EnableClock()  argument
337   WRITE_REG(RCC->MC_AHB2ENSETR, Periphs);  in LL_AHB2_GRP1_EnableClock()
339   tmpreg = READ_BIT(RCC->MC_AHB2ENSETR, Periphs);  in LL_AHB2_GRP1_EnableClock()
360 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_AHB2_GRP1_IsEnabledClock()  argument
362   return (READ_BIT(RCC->MC_AHB2ENSETR, Periphs) == Periphs);  in LL_AHB2_GRP1_IsEnabledClock()
382 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)  in LL_AHB2_GRP1_DisableClock()  argument
384   WRITE_REG(RCC->MC_AHB2ENCLRR, Periphs);  in LL_AHB2_GRP1_DisableClock()
405 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)  in LL_AHB2_GRP1_ForceReset()  argument
407   WRITE_REG(RCC->AHB2RSTSETR, Periphs);  in LL_AHB2_GRP1_ForceReset()
428 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)  in LL_AHB2_GRP1_ReleaseReset()  argument
430   WRITE_REG(RCC->AHB2RSTCLRR, Periphs);  in LL_AHB2_GRP1_ReleaseReset()
450 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_AHB2_GRP1_EnableClockSleep()  argument
453   WRITE_REG(RCC->MC_AHB2LPENSETR, Periphs);  in LL_AHB2_GRP1_EnableClockSleep()
455   tmpreg = READ_BIT(RCC->MC_AHB2LPENSETR, Periphs);  in LL_AHB2_GRP1_EnableClockSleep()
476 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_AHB2_GRP1_DisableClockSleep()  argument
478   WRITE_REG(RCC->MC_AHB2LPENCLRR, Periphs);  in LL_AHB2_GRP1_DisableClockSleep()
510 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)  in LL_AHB3_GRP1_EnableClock()  argument
513   WRITE_REG(RCC->MC_AHB3ENSETR, Periphs);  in LL_AHB3_GRP1_EnableClock()
515   tmpreg = READ_BIT(RCC->MC_AHB3ENSETR, Periphs);  in LL_AHB3_GRP1_EnableClock()
540 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_AHB3_GRP1_IsEnabledClock()  argument
542   return (READ_BIT(RCC->MC_AHB3ENSETR, Periphs) == Periphs);  in LL_AHB3_GRP1_IsEnabledClock()
566 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)  in LL_AHB3_GRP1_DisableClock()  argument
568   WRITE_REG(RCC->MC_AHB3ENCLRR, Periphs);  in LL_AHB3_GRP1_DisableClock()
593 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)  in LL_AHB3_GRP1_ForceReset()  argument
595   WRITE_REG(RCC->AHB3RSTSETR, Periphs);  in LL_AHB3_GRP1_ForceReset()
620 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)  in LL_AHB3_GRP1_ReleaseReset()  argument
622   WRITE_REG(RCC->AHB3RSTCLRR, Periphs);  in LL_AHB3_GRP1_ReleaseReset()
646 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_AHB3_GRP1_EnableClockSleep()  argument
649   WRITE_REG(RCC->MC_AHB3LPENSETR, Periphs);  in LL_AHB3_GRP1_EnableClockSleep()
651   tmpreg = READ_BIT(RCC->MC_AHB3LPENSETR, Periphs);  in LL_AHB3_GRP1_EnableClockSleep()
677 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_AHB3_GRP1_DisableClockSleep()  argument
679   WRITE_REG(RCC->MC_AHB3LPENCLRR, Periphs);  in LL_AHB3_GRP1_DisableClockSleep()
717 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)  in LL_AHB4_GRP1_EnableClock()  argument
720   WRITE_REG(RCC->MC_AHB4ENSETR, Periphs);  in LL_AHB4_GRP1_EnableClock()
722   tmpreg = READ_BIT(RCC->MC_AHB4ENSETR, Periphs);  in LL_AHB4_GRP1_EnableClock()
753 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_AHB4_GRP1_IsEnabledClock()  argument
755   return (READ_BIT(RCC->MC_AHB4ENSETR, Periphs) == Periphs);  in LL_AHB4_GRP1_IsEnabledClock()
787 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)  in LL_AHB4_GRP1_DisableClock()  argument
789   WRITE_REG(RCC->MC_AHB4ENCLRR, Periphs);  in LL_AHB4_GRP1_DisableClock()
819 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)  in LL_AHB4_GRP1_ForceReset()  argument
821   WRITE_REG(RCC->AHB4RSTSETR, Periphs);  in LL_AHB4_GRP1_ForceReset()
851 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)  in LL_AHB4_GRP1_ReleaseReset()  argument
853   WRITE_REG(RCC->AHB4RSTCLRR, Periphs);  in LL_AHB4_GRP1_ReleaseReset()
885 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_AHB4_GRP1_EnableClockSleep()  argument
888   WRITE_REG(RCC->MC_AHB4LPENSETR, Periphs);  in LL_AHB4_GRP1_EnableClockSleep()
890   tmpreg = READ_BIT(RCC->MC_AHB4LPENSETR, Periphs);  in LL_AHB4_GRP1_EnableClockSleep()
921 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_AHB4_GRP1_DisableClockSleep()  argument
923   WRITE_REG(RCC->MC_AHB4LPENCLRR, Periphs);  in LL_AHB4_GRP1_DisableClockSleep()
951 __STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs)  in LL_AHB5_GRP1_EnableClock()  argument
954   WRITE_REG(RCC->MC_AHB5ENSETR, Periphs);  in LL_AHB5_GRP1_EnableClock()
956   tmpreg = READ_BIT(RCC->MC_AHB5ENSETR, Periphs);  in LL_AHB5_GRP1_EnableClock()
977 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_AHB5_GRP1_IsEnabledClock()  argument
979   return (READ_BIT(RCC->MC_AHB5ENSETR, Periphs) == Periphs);  in LL_AHB5_GRP1_IsEnabledClock()
999 __STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs)  in LL_AHB5_GRP1_DisableClock()  argument
1001   WRITE_REG(RCC->MC_AHB5ENCLRR, Periphs);  in LL_AHB5_GRP1_DisableClock()
1021 __STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs)  in LL_AHB5_GRP1_ForceReset()  argument
1023   WRITE_REG(RCC->AHB5RSTSETR, Periphs);  in LL_AHB5_GRP1_ForceReset()
1043 __STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)  in LL_AHB5_GRP1_ReleaseReset()  argument
1045   WRITE_REG(RCC->AHB5RSTCLRR, Periphs);  in LL_AHB5_GRP1_ReleaseReset()
1065 __STATIC_INLINE void LL_AHB5_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_AHB5_GRP1_EnableClockSleep()  argument
1068   WRITE_REG(RCC->MC_AHB5LPENSETR, Periphs);  in LL_AHB5_GRP1_EnableClockSleep()
1070   tmpreg = READ_BIT(RCC->MC_AHB5LPENSETR, Periphs);  in LL_AHB5_GRP1_EnableClockSleep()
1091 __STATIC_INLINE void LL_AHB5_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_AHB5_GRP1_DisableClockSleep()  argument
1093   WRITE_REG(RCC->MC_AHB5LPENCLRR, Periphs);  in LL_AHB5_GRP1_DisableClockSleep()
1133 __STATIC_INLINE void LL_AHB6_GRP1_EnableClock(uint32_t Periphs)  in LL_AHB6_GRP1_EnableClock()  argument
1136   WRITE_REG(RCC->MC_AHB6ENSETR, Periphs);  in LL_AHB6_GRP1_EnableClock()
1138   tmpreg = READ_BIT(RCC->MC_AHB6ENSETR, Periphs);  in LL_AHB6_GRP1_EnableClock()
1171 __STATIC_INLINE uint32_t LL_AHB6_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_AHB6_GRP1_IsEnabledClock()  argument
1173   return (READ_BIT(RCC->MC_AHB6ENSETR, Periphs) == Periphs);  in LL_AHB6_GRP1_IsEnabledClock()
1205 __STATIC_INLINE void LL_AHB6_GRP1_DisableClock(uint32_t Periphs)  in LL_AHB6_GRP1_DisableClock()  argument
1207   WRITE_REG(RCC->MC_AHB6ENCLRR, Periphs);  in LL_AHB6_GRP1_DisableClock()
1231 __STATIC_INLINE void LL_AHB6_GRP1_ForceReset(uint32_t Periphs)  in LL_AHB6_GRP1_ForceReset()  argument
1233   WRITE_REG(RCC->AHB6RSTSETR, Periphs);  in LL_AHB6_GRP1_ForceReset()
1255 __STATIC_INLINE void LL_AHB6_GRP1_ReleaseReset(uint32_t Periphs)  in LL_AHB6_GRP1_ReleaseReset()  argument
1257   WRITE_REG(RCC->AHB6RSTCLRR, Periphs);  in LL_AHB6_GRP1_ReleaseReset()
1289 __STATIC_INLINE void LL_AHB6_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_AHB6_GRP1_EnableClockSleep()  argument
1292   WRITE_REG(RCC->MC_AHB6LPENSETR, Periphs);  in LL_AHB6_GRP1_EnableClockSleep()
1294   tmpreg = READ_BIT(RCC->MC_AHB6LPENSETR, Periphs);  in LL_AHB6_GRP1_EnableClockSleep()
1327 __STATIC_INLINE void LL_AHB6_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_AHB6_GRP1_DisableClockSleep()  argument
1329   WRITE_REG(RCC->MC_AHB6LPENCLRR, Periphs);  in LL_AHB6_GRP1_DisableClockSleep()
1339 __STATIC_INLINE void LL_AHB6_GRP1_EnableClockStop(uint32_t Periphs)  in LL_AHB6_GRP1_EnableClockStop()  argument
1342   WRITE_REG(RCC->MC_AHB6LPENSETR, Periphs);  in LL_AHB6_GRP1_EnableClockStop()
1344   tmpreg = READ_BIT(RCC->MC_AHB6LPENSETR, Periphs);  in LL_AHB6_GRP1_EnableClockStop()
1355 __STATIC_INLINE void LL_AHB6_GRP1_DisableClockStop(uint32_t Periphs)  in LL_AHB6_GRP1_DisableClockStop()  argument
1357   WRITE_REG(RCC->MC_AHB6LPENCLRR, Periphs);  in LL_AHB6_GRP1_DisableClockStop()
1375 __STATIC_INLINE void LL_AXI_GRP1_EnableClock(uint32_t Periphs)  in LL_AXI_GRP1_EnableClock()  argument
1378   WRITE_REG(RCC->MC_AXIMENSETR, Periphs);  in LL_AXI_GRP1_EnableClock()
1380   tmpreg = READ_BIT(RCC->MC_AXIMENSETR, Periphs);  in LL_AXI_GRP1_EnableClock()
1391 __STATIC_INLINE uint32_t LL_AXI_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_AXI_GRP1_IsEnabledClock()  argument
1393   return (READ_BIT(RCC->MC_AXIMENSETR, Periphs) == Periphs);  in LL_AXI_GRP1_IsEnabledClock()
1403 __STATIC_INLINE void LL_AXI_GRP1_DisableClock(uint32_t Periphs)  in LL_AXI_GRP1_DisableClock()  argument
1405   WRITE_REG(RCC->MC_AXIMENCLRR, Periphs);  in LL_AXI_GRP1_DisableClock()
1415 __STATIC_INLINE void LL_AXI_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_AXI_GRP1_EnableClockSleep()  argument
1418   WRITE_REG(RCC->MC_AXIMLPENSETR, Periphs);  in LL_AXI_GRP1_EnableClockSleep()
1420   tmpreg = READ_BIT(RCC->MC_AXIMLPENSETR, Periphs);  in LL_AXI_GRP1_EnableClockSleep()
1431 __STATIC_INLINE void LL_AXI_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_AXI_GRP1_DisableClockSleep()  argument
1433   WRITE_REG(RCC->MC_AXIMLPENCLRR, Periphs);  in LL_AXI_GRP1_DisableClockSleep()
1451 __STATIC_INLINE void LL_MLAHB_GRP1_EnableClock(uint32_t Periphs)  in LL_MLAHB_GRP1_EnableClock()  argument
1454   WRITE_REG(RCC->MC_MLAHBENSETR, Periphs);  in LL_MLAHB_GRP1_EnableClock()
1456   tmpreg = READ_BIT(RCC->MC_MLAHBENSETR, Periphs);  in LL_MLAHB_GRP1_EnableClock()
1467 __STATIC_INLINE uint32_t LL_MLAHB_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_MLAHB_GRP1_IsEnabledClock()  argument
1469   return (READ_BIT(RCC->MC_MLAHBENSETR, Periphs) == Periphs);  in LL_MLAHB_GRP1_IsEnabledClock()
1479 __STATIC_INLINE void LL_MLAHB_GRP1_DisableClock(uint32_t Periphs)  in LL_MLAHB_GRP1_DisableClock()  argument
1481   WRITE_REG(RCC->MC_MLAHBENCLRR, Periphs);  in LL_MLAHB_GRP1_DisableClock()
1491 __STATIC_INLINE void LL_MLAHB_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_MLAHB_GRP1_EnableClockSleep()  argument
1494   WRITE_REG(RCC->MC_MLAHBLPENSETR, Periphs);  in LL_MLAHB_GRP1_EnableClockSleep()
1496   tmpreg = READ_BIT(RCC->MC_MLAHBLPENSETR, Periphs);  in LL_MLAHB_GRP1_EnableClockSleep()
1507 __STATIC_INLINE void LL_MLAHB_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_MLAHB_GRP1_DisableClockSleep()  argument
1509   WRITE_REG(RCC->MC_MLAHBLPENCLRR, Periphs);  in LL_MLAHB_GRP1_DisableClockSleep()
1579 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)  in LL_APB1_GRP1_EnableClock()  argument
1582   WRITE_REG(RCC->MC_APB1ENSETR, Periphs);  in LL_APB1_GRP1_EnableClock()
1584   tmpreg = READ_BIT(RCC->MC_APB1ENSETR, Periphs);  in LL_APB1_GRP1_EnableClock()
1647 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_APB1_GRP1_IsEnabledClock()  argument
1649   return (READ_BIT(RCC->MC_APB1ENSETR, Periphs) == Periphs);  in LL_APB1_GRP1_IsEnabledClock()
1709 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)  in LL_APB1_GRP1_DisableClock()  argument
1711   WRITE_REG(RCC->MC_APB1ENCLRR, Periphs);  in LL_APB1_GRP1_DisableClock()
1771 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)  in LL_APB1_GRP1_ForceReset()  argument
1773   WRITE_REG(RCC->APB1RSTSETR, Periphs);  in LL_APB1_GRP1_ForceReset()
1833 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)  in LL_APB1_GRP1_ReleaseReset()  argument
1835   WRITE_REG(RCC->APB1RSTCLRR, Periphs);  in LL_APB1_GRP1_ReleaseReset()
1897 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_APB1_GRP1_EnableClockSleep()  argument
1900   WRITE_REG(RCC->MC_APB1LPENSETR, Periphs);  in LL_APB1_GRP1_EnableClockSleep()
1902   tmpreg = READ_BIT(RCC->MC_APB1LPENSETR, Periphs);  in LL_APB1_GRP1_EnableClockSleep()
1965 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_APB1_GRP1_DisableClockSleep()  argument
1967   WRITE_REG(RCC->MC_APB1LPENCLRR, Periphs);  in LL_APB1_GRP1_DisableClockSleep()
2013 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)  in LL_APB2_GRP1_EnableClock()  argument
2016   WRITE_REG(RCC->MC_APB2ENSETR, Periphs);  in LL_APB2_GRP1_EnableClock()
2018   tmpreg = READ_BIT(RCC->MC_APB2ENSETR, Periphs);  in LL_APB2_GRP1_EnableClock()
2057 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_APB2_GRP1_IsEnabledClock()  argument
2059   return (READ_BIT(RCC->MC_APB2ENSETR, Periphs) == Periphs);  in LL_APB2_GRP1_IsEnabledClock()
2097 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)  in LL_APB2_GRP1_DisableClock()  argument
2099   WRITE_REG(RCC->MC_APB2ENCLRR, Periphs);  in LL_APB2_GRP1_DisableClock()
2136 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)  in LL_APB2_GRP1_ForceReset()  argument
2138   WRITE_REG(RCC->APB2RSTSETR, Periphs);  in LL_APB2_GRP1_ForceReset()
2175 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)  in LL_APB2_GRP1_ReleaseReset()  argument
2177   WRITE_REG(RCC->APB2RSTCLRR, Periphs);  in LL_APB2_GRP1_ReleaseReset()
2215 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_APB2_GRP1_EnableClockSleep()  argument
2218   WRITE_REG(RCC->MC_APB2LPENSETR, Periphs);  in LL_APB2_GRP1_EnableClockSleep()
2220   tmpreg = READ_BIT(RCC->MC_APB2LPENSETR, Periphs);  in LL_APB2_GRP1_EnableClockSleep()
2259 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_APB2_GRP1_DisableClockSleep()  argument
2261   WRITE_REG(RCC->MC_APB2LPENCLRR, Periphs);  in LL_APB2_GRP1_DisableClockSleep()
2296 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)  in LL_APB3_GRP1_EnableClock()  argument
2299   WRITE_REG(RCC->MC_APB3ENSETR, Periphs);  in LL_APB3_GRP1_EnableClock()
2301   tmpreg = READ_BIT(RCC->MC_APB3ENSETR, Periphs);  in LL_APB3_GRP1_EnableClock()
2329 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_APB3_GRP1_IsEnabledClock()  argument
2331   return (READ_BIT(RCC->MC_APB3ENSETR, Periphs) == Periphs);  in LL_APB3_GRP1_IsEnabledClock()
2358 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)  in LL_APB3_GRP1_DisableClock()  argument
2360   WRITE_REG(RCC->MC_APB3ENCLRR, Periphs);  in LL_APB3_GRP1_DisableClock()
2386 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)  in LL_APB3_GRP1_ForceReset()  argument
2388   WRITE_REG(RCC->APB3RSTSETR, Periphs);  in LL_APB3_GRP1_ForceReset()
2414 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)  in LL_APB3_GRP1_ReleaseReset()  argument
2416   WRITE_REG(RCC->APB3RSTCLRR, Periphs);  in LL_APB3_GRP1_ReleaseReset()
2442 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_APB3_GRP1_EnableClockSleep()  argument
2445   WRITE_REG(RCC->MC_APB3LPENSETR, Periphs);  in LL_APB3_GRP1_EnableClockSleep()
2447   tmpreg = READ_BIT(RCC->MC_APB3LPENSETR, Periphs);  in LL_APB3_GRP1_EnableClockSleep()
2473 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_APB3_GRP1_DisableClockSleep()  argument
2475   WRITE_REG(RCC->MC_APB3LPENCLRR, Periphs);  in LL_APB3_GRP1_DisableClockSleep()
2501 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)  in LL_APB4_GRP1_EnableClock()  argument
2504   WRITE_REG(RCC->MC_APB4ENSETR, Periphs);  in LL_APB4_GRP1_EnableClock()
2506   tmpreg = READ_BIT(RCC->MC_APB4ENSETR, Periphs);  in LL_APB4_GRP1_EnableClock()
2525 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_APB4_GRP1_IsEnabledClock()  argument
2527   return (READ_BIT(RCC->MC_APB4ENSETR, Periphs) == Periphs);  in LL_APB4_GRP1_IsEnabledClock()
2545 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)  in LL_APB4_GRP1_DisableClock()  argument
2547   WRITE_REG(RCC->MC_APB4ENCLRR, Periphs);  in LL_APB4_GRP1_DisableClock()
2564 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)  in LL_APB4_GRP1_ForceReset()  argument
2566   WRITE_REG(RCC->APB4RSTSETR, Periphs);  in LL_APB4_GRP1_ForceReset()
2583 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)  in LL_APB4_GRP1_ReleaseReset()  argument
2585   WRITE_REG(RCC->APB4RSTCLRR, Periphs);  in LL_APB4_GRP1_ReleaseReset()
2603 __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_APB4_GRP1_EnableClockSleep()  argument
2606   WRITE_REG(RCC->MC_APB4LPENSETR, Periphs);  in LL_APB4_GRP1_EnableClockSleep()
2608   tmpreg = READ_BIT(RCC->MC_APB4LPENSETR, Periphs);  in LL_APB4_GRP1_EnableClockSleep()
2627 __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_APB4_GRP1_DisableClockSleep()  argument
2629   WRITE_REG(RCC->MC_APB4LPENCLRR, Periphs);  in LL_APB4_GRP1_DisableClockSleep()
2639 __STATIC_INLINE void LL_APB4_GRP1_EnableClockStop(uint32_t Periphs)  in LL_APB4_GRP1_EnableClockStop()  argument
2642   WRITE_REG(RCC->MC_APB4LPENSETR, Periphs);  in LL_APB4_GRP1_EnableClockStop()
2644   tmpreg = READ_BIT(RCC->MC_APB4LPENSETR, Periphs);  in LL_APB4_GRP1_EnableClockStop()
2655 __STATIC_INLINE void LL_APB4_GRP1_DisableClockStop(uint32_t Periphs)  in LL_APB4_GRP1_DisableClockStop()  argument
2657   WRITE_REG(RCC->MC_APB4LPENCLRR, Periphs);  in LL_APB4_GRP1_DisableClockStop()
2693 __STATIC_INLINE void LL_APB5_GRP1_EnableClock(uint32_t Periphs)  in LL_APB5_GRP1_EnableClock()  argument
2696   WRITE_REG(RCC->MC_APB5ENSETR, Periphs);  in LL_APB5_GRP1_EnableClock()
2698   tmpreg = READ_BIT(RCC->MC_APB5ENSETR, Periphs);  in LL_APB5_GRP1_EnableClock()
2727 __STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_APB5_GRP1_IsEnabledClock()  argument
2729   return (READ_BIT(RCC->MC_APB5ENSETR, Periphs) == Periphs);  in LL_APB5_GRP1_IsEnabledClock()
2757 __STATIC_INLINE void LL_APB5_GRP1_DisableClock(uint32_t Periphs)  in LL_APB5_GRP1_DisableClock()  argument
2759   WRITE_REG(RCC->MC_APB5ENCLRR, Periphs);  in LL_APB5_GRP1_DisableClock()
2778 __STATIC_INLINE void LL_APB5_GRP1_ForceReset(uint32_t Periphs)  in LL_APB5_GRP1_ForceReset()  argument
2780   WRITE_REG(RCC->APB5RSTSETR, Periphs);  in LL_APB5_GRP1_ForceReset()
2799 __STATIC_INLINE void LL_APB5_GRP1_ReleaseReset(uint32_t Periphs)  in LL_APB5_GRP1_ReleaseReset()  argument
2801   WRITE_REG(RCC->APB5RSTCLRR, Periphs);  in LL_APB5_GRP1_ReleaseReset()
2829 __STATIC_INLINE void LL_APB5_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_APB5_GRP1_EnableClockSleep()  argument
2832   WRITE_REG(RCC->MC_APB5LPENSETR, Periphs);  in LL_APB5_GRP1_EnableClockSleep()
2834   tmpreg = READ_BIT(RCC->MC_APB5LPENSETR, Periphs);  in LL_APB5_GRP1_EnableClockSleep()
2863 __STATIC_INLINE void LL_APB5_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_APB5_GRP1_DisableClockSleep()  argument
2865   WRITE_REG(RCC->MC_APB5LPENCLRR, Periphs);  in LL_APB5_GRP1_DisableClockSleep()
2875 __STATIC_INLINE void LL_APB5_GRP1_EnableClockStop(uint32_t Periphs)  in LL_APB5_GRP1_EnableClockStop()  argument
2878   WRITE_REG(RCC->MC_APB5LPENSETR, Periphs);  in LL_APB5_GRP1_EnableClockStop()
2880   tmpreg = READ_BIT(RCC->MC_APB5LPENSETR, Periphs);  in LL_APB5_GRP1_EnableClockStop()
2891 __STATIC_INLINE void LL_APB5_GRP1_DisableClockStop(uint32_t Periphs)  in LL_APB5_GRP1_DisableClockStop()  argument
2893   WRITE_REG(RCC->MC_APB5LPENCLRR, Periphs);  in LL_APB5_GRP1_DisableClockStop()