Lines Matching refs:MODIFY_REG
546 #define __HAL_HDP0_SELECT_PWR_PWRWAKE_SYS() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
547 #define __HAL_HDP0_SELECT_CM4_SLEEPDEEP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
548 #define __HAL_HDP0_SELECT_PWR_STDBY_WKUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
549 #define __HAL_HDP0_SELECT_PWR_ENCOMP_VDDCORE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
550 #define __HAL_HDP0_SELECT_BSEC_OUT_SEC_NIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
551 #define __HAL_HDP0_SELECT_RCC_CM4_SLEEPDEEP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
552 #define __HAL_HDP0_SELECT_GPU_DBG7() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
553 #define __HAL_HDP0_SELECT_DDRCTRL_IP_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
554 #define __HAL_HDP0_SELECT_PWR_DDR_RET_ENABLE_N() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
555 #define __HAL_HDP0_SELECT_GPOVAL_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
564 #define __HAL_HDP1_SELECT_PWR_PWRWAKE_MCU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
565 #define __HAL_HDP1_SELECT_CM4_HALTED() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
566 #define __HAL_HDP1_SELECT_CA7_nAXIERRIRQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
567 #define __HAL_HDP1_SELECT_PWR_OKIN_MR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
568 #define __HAL_HDP1_SELECT_BSEC_OUT_SEC_DBGEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
569 #define __HAL_HDP1_SELECT_EXTI_SYS_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
570 #define __HAL_HDP1_SELECT_RCC_PWRDS_MPU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
571 #define __HAL_HDP1_SELECT_GPU_DBG6() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
572 #define __HAL_HDP1_SELECT_DDRCTRL_DFI_CTRLUPD_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
573 #define __HAL_HDP1_SELECT_DDRCTRL_CACTIVE_DDRC_ASR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
574 #define __HAL_HDP1_SELECT_GPOVAL_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
583 #define __HAL_HDP2_SELECT_PWR_PWRWAKE_MPU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
584 #define __HAL_HDP2_SELECT_CM4_RXEV() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
585 #define __HAL_HDP2_SELECT_CA7_nPMUIRQ1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
586 #define __HAL_HDP2_SELECT_CA7_nFIQOUT1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
587 #define __HAL_HDP2_SELECT_BSEC_IN_RSTCORE_n() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
588 #define __HAL_HDP2_SELECT_EXTI_C2_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
589 #define __HAL_HDP2_SELECT_RCC_PWRDS_MCU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
590 #define __HAL_HDP2_SELECT_GPU_DBG5() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
591 #define __HAL_HDP2_SELECT_DDRCTRL_DFI_INIT_COMPLETE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
592 #define __HAL_HDP2_SELECT_DDRCTRL_PERF_OP_IS_REFRESH() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
593 #define __HAL_HDP2_SELECT_DDRCTRL_GSKP_DFI_LP_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
594 #define __HAL_HDP2_SELECT_GPOVAL_2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
603 #define __HAL_HDP3_SELECT_PWR_SEL_VTH_VDD_CORE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
604 #define __HAL_HDP3_SELECT_CM4_TXEV() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
605 #define __HAL_HDP3_SELECT_CA7_nPMUIRQ0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
606 #define __HAL_HDP3_SELECT_CA7_nFIQOUT0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
607 #define __HAL_HDP3_SELECT_BSEC_OUT_SEC_DFTLOCK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
608 #define __HAL_HDP3_SELECT_EXTI_C1_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
609 #define __HAL_HDP3_SELECT_RCC_PWRDS_SYS() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
610 #define __HAL_HDP3_SELECT_GPU_DBG4() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
611 #define __HAL_HDP3_SELECT_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
612 #define __HAL_HDP3_SELECT_DDRCTRL_CACTIVE_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
613 #define __HAL_HDP3_SELECT_GPOVAL_3() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
622 #define __HAL_HDP4_SELECT_PWR_MPUCR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
623 #define __HAL_HDP4_SELECT_CM4_SLEEPING() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
624 #define __HAL_HDP4_SELECT_CA7_nRESET1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
625 #define __HAL_HDP4_SELECT_CA7_nIRQOUT1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
626 #define __HAL_HDP4_SELECT_BSEC_OUT_SEC_DFTEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
627 #define __HAL_HDP4_SELECT_BSEC_OUT_SEC_DBGSWENABLE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
628 #define __HAL_HDP4_SELECT_ETH_OUT_PMT_INTR_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
629 #define __HAL_HDP4_SELECT_GPU_DBG3() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
630 #define __HAL_HDP4_SELECT_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
631 #define __HAL_HDP4_SELECT_DDRCTRL_CACTIVE_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
632 #define __HAL_HDP4_SELECT_GPOVAL_4() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
641 #define __HAL_HDP5_SELECT_CA7_STANDBYWFIL2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
642 #define __HAL_HDP5_SELECT_PWR_VTH_VDDCORE_ACK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
643 #define __HAL_HDP5_SELECT_CA7_nRESET0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
644 #define __HAL_HDP5_SELECT_CA7_nIRQOUT0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
645 #define __HAL_HDP5_SELECT_BSEC_IN_PWROK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
646 #define __HAL_HDP5_SELECT_BSEC_OUT_SEC_DEVICEEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
647 #define __HAL_HDP5_SELECT_ETH_OUT_LPI_INTR_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
648 #define __HAL_HDP5_SELECT_GPU_DBG2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
649 #define __HAL_HDP5_SELECT_DDRCTRL_CACTIVE_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
650 #define __HAL_HDP5_SELECT_DDRCTRL_WR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
651 #define __HAL_HDP5_SELECT_GPOVAL_5() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
659 #define __HAL_HDP6_SELECT_CA7_STANDBYWFI1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
660 #define __HAL_HDP6_SELECT_CA7_STANDBYWFE1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
661 #define __HAL_HDP6_SELECT_CA7_EVENTO() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
662 #define __HAL_HDP6_SELECT_CA7_DBGACK1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
663 #define __HAL_HDP6_SELECT_BSEC_OUT_SEC_SPNIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
664 #define __HAL_HDP6_SELECT_ETH_OUT_MAC_SPEED_O1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
665 #define __HAL_HDP6_SELECT_GPU_DBG1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
666 #define __HAL_HDP6_SELECT_DDRCTRL_CSYSACK_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
667 #define __HAL_HDP6_SELECT_DDRCTRL_LPR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
668 #define __HAL_HDP6_SELECT_GPOVAL_6() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
677 #define __HAL_HDP7_SELECT_CA7_STANDBYWFI0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
678 #define __HAL_HDP7_SELECT_CA7_STANDBYWFE0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
679 #define __HAL_HDP7_SELECT_CA7_DBGACK0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
680 #define __HAL_HDP7_SELECT_BSEC_OUT_FUSE_OK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
681 #define __HAL_HDP7_SELECT_BSEC_OUT_SEC_SPIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
682 #define __HAL_HDP7_SELECT_ETH_OUT_MAC_SPEED_O0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
683 #define __HAL_HDP7_SELECT_GPU_DBG0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
684 #define __HAL_HDP7_SELECT_DDRCTRL_CSYSREQ_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
685 #define __HAL_HDP7_SELECT_DDRCTRL_HPR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…
686 #define __HAL_HDP7_SELECT_GPOVAL_7() MODIFY_REG(HDP->HDP_MUX, HDP_MUX…