173 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Init()  argument
181   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Init()
201   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);  in FMC_NORSRAM_Init()
250   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);  in FMC_NORSRAM_Init()
255     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);  in FMC_NORSRAM_Init()
261     SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));  in FMC_NORSRAM_Init()
271     MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime));  in FMC_NORSRAM_Init()
277         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);  in FMC_NORSRAM_Init()
281         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);  in FMC_NORSRAM_Init()
285         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);  in FMC_NORSRAM_Init()
289         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);  in FMC_NORSRAM_Init()
304 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_DeInit()  argument
308   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_DeInit()
313   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
319     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
324     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
327   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
334       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);  in FMC_NORSRAM_DeInit()
338       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);  in FMC_NORSRAM_DeInit()
342       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);  in FMC_NORSRAM_DeInit()
346       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);  in FMC_NORSRAM_DeInit()
361 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Timing_Init()  argument
367   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Timing_Init()
379   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
390   if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))  in FMC_NORSRAM_Timing_Init()
392     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));  in FMC_NORSRAM_Timing_Init()
394     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);  in FMC_NORSRAM_Timing_Init()
412 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,  in FMC_NORSRAM_Extended_Timing_Init()  argument
423     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));  in FMC_NORSRAM_Extended_Timing_Init()
433 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
442     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
472 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
475   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Enable()
479   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
490 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
493   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Disable()
497   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
560 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)  in FMC_NAND_Init()  argument
563   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_Init()
573   MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                            |  in FMC_NAND_Init()
592 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_CommonSpace_Timing_Init()  argument
596   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_CommonSpace_Timing_Init()
607   Device->PMEM =(Timing->SetupTime  |  in FMC_NAND_CommonSpace_Timing_Init()
623 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_AttributeSpace_Timing_Init()  argument
627   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_AttributeSpace_Timing_Init()
638   Device->PATT =(Timing->SetupTime |  in FMC_NAND_AttributeSpace_Timing_Init()
652 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
655   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_DeInit()
659   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
666   WRITE_REG(Device->PCR,  0x00000018U);  in FMC_NAND_DeInit()
667   WRITE_REG(Device->SR,   0x00000040U);  in FMC_NAND_DeInit()
668   WRITE_REG(Device->PMEM, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
669   WRITE_REG(Device->PATT, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
700 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
703   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Enable()
710   SET_BIT(Device->PCR, FMC_PCR_ECCEN);  in FMC_NAND_ECC_Enable()
722 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
725   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Disable()
732   CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);  in FMC_NAND_ECC_Disable()
745 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
751   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_GetECC()
758   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
774   *ECCval = (uint32_t)Device->ECCR;  in FMC_NAND_GetECC()