92 #if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED)
177   if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)  in HAL_ICACHE_ConfigAssociativityMode()
183     MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode);  in HAL_ICACHE_ConfigAssociativityMode()
196   WRITE_REG(ICACHE->IER, 0U);  in HAL_ICACHE_DeInit()
199   WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);  in HAL_ICACHE_DeInit()
202   CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);  in HAL_ICACHE_DeInit()
203   WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);  in HAL_ICACHE_DeInit()
206   CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS);  in HAL_ICACHE_DeInit()
207   SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));  in HAL_ICACHE_DeInit()
208   CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));  in HAL_ICACHE_DeInit()
211   WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);  in HAL_ICACHE_DeInit()
212   WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);  in HAL_ICACHE_DeInit()
213   WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);  in HAL_ICACHE_DeInit()
214   WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);  in HAL_ICACHE_DeInit()
228   SET_BIT(ICACHE->CR, ICACHE_CR_EN);  in HAL_ICACHE_Enable()
246   WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);  in HAL_ICACHE_Disable()
248   CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);  in HAL_ICACHE_Disable()
254   while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)  in HAL_ICACHE_Disable()
259       if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)  in HAL_ICACHE_Disable()
276   return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL);  in HAL_ICACHE_IsEnabled()
290   if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U)  in HAL_ICACHE_Invalidate()
293     SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);  in HAL_ICACHE_Invalidate()
314   if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)  in HAL_ICACHE_Invalidate_IT()
321     WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);  in HAL_ICACHE_Invalidate_IT()
324     SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);  in HAL_ICACHE_Invalidate_IT()
327     SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);  in HAL_ICACHE_Invalidate_IT()
344   if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)  in HAL_ICACHE_WaitForInvalidateComplete()
350     while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)  in HAL_ICACHE_WaitForInvalidateComplete()
355         if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)  in HAL_ICACHE_WaitForInvalidateComplete()
365   WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);  in HAL_ICACHE_WaitForInvalidateComplete()
385   SET_BIT(ICACHE->CR, MonitorType);  in HAL_ICACHE_Monitor_Start()
405   CLEAR_BIT(ICACHE->CR, MonitorType);  in HAL_ICACHE_Monitor_Stop()
425   SET_BIT(ICACHE->CR, (MonitorType << 2U));  in HAL_ICACHE_Monitor_Reset()
426   CLEAR_BIT(ICACHE->CR, (MonitorType << 2U));  in HAL_ICACHE_Monitor_Reset()
438   return (ICACHE->HMONR);  in HAL_ICACHE_Monitor_GetHitValue()
448   return (ICACHE->MMONR);  in HAL_ICACHE_Monitor_GetMissValue()
479   uint32_t itflags   = READ_REG(ICACHE->SR);  in HAL_ICACHE_IRQHandler()
480   uint32_t itsources = READ_REG(ICACHE->IER);  in HAL_ICACHE_IRQHandler()
486     CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);  in HAL_ICACHE_IRQHandler()
489     WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);  in HAL_ICACHE_IRQHandler()
499     CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);  in HAL_ICACHE_IRQHandler()
502     WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);  in HAL_ICACHE_IRQHandler()
568   if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)  in HAL_ICACHE_EnableRemapRegion()
575     p_reg = &(ICACHE->CRR0) + (1U * Region);  in HAL_ICACHE_EnableRemapRegion()
619   if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)  in HAL_ICACHE_DisableRemapRegion()
626     p_reg = &(ICACHE->CRR0) + (1U * Region);  in HAL_ICACHE_DisableRemapRegion()