Lines Matching refs:PWR
33 #if defined(PWR)
164 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
165 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
166 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
167 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
168 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
169 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
170 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
171 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
257 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
264 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
290 SET_BIT(PWR->CR1, PWR_CR1_LPR); in LL_PWR_EnableLowPowerRunMode()
300 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); in LL_PWR_DisableLowPowerRunMode()
310 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL); in LL_PWR_IsEnabledLowPowerRunMode()
344 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
357 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); in LL_PWR_GetRegulVoltageScaling()
367 SET_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_EnableBkUpAccess()
377 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_DisableBkUpAccess()
387 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpAccess()
403 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); in LL_PWR_SetPowerMode()
418 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); in LL_PWR_GetPowerMode()
429 SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); in LL_PWR_EnableUCPDStandbyMode()
441 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); in LL_PWR_DisableUCPDStandbyMode()
452 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY)) ? 1UL : 0UL); in LL_PWR_IsEnabledUCPDStandbyMode()
468 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); in LL_PWR_EnableUCPDDeadBattery()
483 SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); in LL_PWR_DisableUCPDDeadBattery()
498 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL); in LL_PWR_IsEnabledUCPDDeadBattery()
508 SET_BIT(PWR->CR2, PWR_CR2_USV); in LL_PWR_EnableVddUSB()
518 CLEAR_BIT(PWR->CR2, PWR_CR2_USV); in LL_PWR_DisableVddUSB()
528 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddUSB()
538 SET_BIT(PWR->CR2, PWR_CR2_IOSV); in LL_PWR_EnableVddIO2()
548 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); in LL_PWR_DisableVddIO2()
558 return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO2()
576 SET_BIT(PWR->CR2, PeriphVoltage); in LL_PWR_EnablePVM()
594 CLEAR_BIT(PWR->CR2, PeriphVoltage); in LL_PWR_DisablePVM()
612 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVM()
631 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); in LL_PWR_SetPVDLevel()
649 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); in LL_PWR_GetPVDLevel()
659 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
669 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
679 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
689 SET_BIT(PWR->CR4, PWR_CR4_SMPSLPEN); in LL_PWR_EnableSMPSLowPowerMode()
699 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSLPEN); in LL_PWR_DisableSMPSLowPowerMode()
709 return ((READ_BIT(PWR->CR4, PWR_CR4_SMPSLPEN) == (PWR_CR4_SMPSLPEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledSMPSLowPowerMode()
719 SET_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN); in LL_PWR_EnableSMPSFastStart()
729 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN); in LL_PWR_DisableSMPSFastStart()
739 return ((READ_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN) == (PWR_CR4_SMPSFSTEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledSMPSFastStart()
749 SET_BIT(PWR->CR4, PWR_CR4_SMPSBYP); in LL_PWR_EnableSMPSBypassMode()
759 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSBYP); in LL_PWR_DisableSMPSBypassMode()
769 return ((READ_BIT(PWR->CR4, PWR_CR4_SMPSBYP) == (PWR_CR4_SMPSBYP)) ? 1UL : 0UL); in LL_PWR_IsEnabledSMPSBypassMode()
779 SET_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN); in LL_PWR_EnableExtSMPS()
789 CLEAR_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN); in LL_PWR_DisableExtSMPS()
799 return ((READ_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN) == (PWR_CR4_EXTSMPSEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledExtSMPS()
809 SET_BIT(PWR->CR3, PWR_CR3_ULPMEN); in LL_PWR_EnableUltraLowPowerMode()
819 CLEAR_BIT(PWR->CR3, PWR_CR3_ULPMEN); in LL_PWR_DisableUltraLowPowerMode()
829 return ((READ_BIT(PWR->CR3, PWR_CR3_ULPMEN) == (PWR_CR3_ULPMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledUltraLowPowerMode()
839 SET_BIT(PWR->CR3, PWR_CR3_APC); in LL_PWR_EnablePUPDCfg()
849 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); in LL_PWR_DisablePUPDCfg()
859 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); in LL_PWR_IsEnabledPUPDCfg()
873 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2Retention); in LL_PWR_SetSRAM2Retention()
886 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS)); in LL_PWR_GetSRAM2Retention()
906 SET_BIT(PWR->CR3, WakeUpPin); in LL_PWR_EnableWakeUpPin()
926 CLEAR_BIT(PWR->CR3, WakeUpPin); in LL_PWR_DisableWakeUpPin()
946 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
959 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
971 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); in LL_PWR_GetBattChargResistor()
981 SET_BIT(PWR->CR4, PWR_CR4_VBE); in LL_PWR_EnableBatteryCharging()
991 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); in LL_PWR_DisableBatteryCharging()
1001 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL); in LL_PWR_IsEnabledBatteryCharging()
1021 SET_BIT(PWR->CR4, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityLow()
1041 CLEAR_BIT(PWR->CR4, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityHigh()
1061 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsWakeUpPinPolarityLow()
1337 return ((READ_BIT(PWR->SR1, PWR_SR1_SMPSHPRDY) == (PWR_SR1_SMPSHPRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SMPSHPRDY()
1347 return ((READ_BIT(PWR->SR1, PWR_SR1_EXTSMPSRDY) == (PWR_SR1_EXTSMPSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_EXTSMPSRDY()
1357 return ((READ_BIT(PWR->SR1, PWR_SR1_SMPSBYPRDY) == (PWR_SR1_SMPSBYPRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SMPSBYPRDY()
1367 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SB()
1377 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU5()
1387 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU4()
1397 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
1407 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
1417 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
1427 WRITE_REG(PWR->SCR, PWR_SCR_CSBF); in LL_PWR_ClearFlag_SB()
1437 WRITE_REG(PWR->SCR, PWR_SCR_CWUF); in LL_PWR_ClearFlag_WU()
1447 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); in LL_PWR_ClearFlag_WU5()
1457 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); in LL_PWR_ClearFlag_WU4()
1467 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); in LL_PWR_ClearFlag_WU3()
1477 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); in LL_PWR_ClearFlag_WU2()
1487 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); in LL_PWR_ClearFlag_WU1()
1497 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVMO4()
1507 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVMO3()
1517 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVMO2()
1527 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVMO1()
1537 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
1547 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
1558 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPF()
1568 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPS()
1586 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV); in LL_PWR_EnablePrivilege()
1596 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV); in LL_PWR_DisablePrivilege()
1606 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV) == PWR_PRIVCFGR_PRIV) ? 1UL : 0UL); in LL_PWR_IsEnabledPrivilege()
1648 WRITE_REG(PWR->SECCFGR, Configuration); in LL_PWR_ConfigSecure()
1678 return (uint32_t)(READ_REG(PWR->SECCFGR)); in LL_PWR_GetConfigSecure()