Lines Matching full:mode
54 …uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to acces…
55 … quad mode on two different devices to increase the throughput.
133 used for memory-mapped mode).
140 uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
144 uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase.
148 uint32_t AddressMode; /*!< It indicates the mode of the address.
152 uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase.
156 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
160 …uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes ph…
162 uint32_t DataMode; /*!< It indicates the mode of the data.
165 This field is only used for indirect mode.
167 uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase.
173 uint32_t SIOOMode; /*!< It enables or not the SIOO mode.
188 uint32_t LatencyMode; /*!< It configures the latency mode.
204 This field is only used for indirect mode.
206 … In case of autopolling mode, this parameter can be any value between 1 and 4 */
212 * @brief HAL OSPI Auto Polling mode configuration structure definition
229 * @brief HAL OSPI Memory Mapped mode configuration structure definition
279 … ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configur…
314 … ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */
315 … ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */
323 … ((uint32_t)0x00000000U) /*!< Micron mode */
324 … ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */
325 … ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */
326 …AM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */
327 … ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
341 /** @defgroup OSPI_ClockMode OSPI Clock Mode
392 … /*!< Common configuration (indirect or auto-polling mode) */
393 … /*!< Read configuration (memory-mapped mode) */
394 … /*!< Write configuration (memory-mapped mode) */
395 … /*!< Wrap configuration (memory-mapped mode) */
409 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode
432 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode
435 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for instru…
436 … ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruc…
441 /** @defgroup OSPI_AddressMode OSPI Address Mode
464 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode
467 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for addres…
468 … ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address…
473 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode
496 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode
499 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for altern…
500 … ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alterna…
505 /** @defgroup OSPI_DataMode OSPI Data Mode
517 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode
520 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for data p…
521 … ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data ph…
526 /** @defgroup OSPI_DQSMode OSPI DQS Mode
535 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode
553 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode
565 … ((uint32_t)0x00000000U) /*!< HyperBus memory mode */
566 … ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
571 /** @defgroup OSPI_MatchMode OSPI Match Mode
574 …t32_t)0x00000000U) /*!< AND match mode between unmasked bi…
575 …nt32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bi…
602 … /*!< Timeout flag: timeout occurs in memory-mapped mode …
603 … /*!< Status match flag: received data matches in autopolling mode …
769 /* OSPI indirect mode functions */
777 /* OSPI status flag polling mode functions */
781 /* OSPI memory-mapped mode functions */
789 /* OSPI indirect mode functions */
796 /* OSPI status flag polling mode functions */
799 /* OSPI memory-mapped mode functions */
839 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ argument
840 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
855 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ argument
856 ((MODE) == HAL_OSPI_CLOCK_MODE_3))
880 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ argument
881 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \
882 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \
883 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \
884 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))
891 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ argument
892 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
894 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ argument
895 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \
896 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \
897 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \
898 ((MODE) == HAL_OSPI_ADDRESS_8_LINES))
905 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ argument
906 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))
908 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ argument
909 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \
910 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \
911 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \
912 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))
919 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ argument
920 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))
922 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ argument
923 ((MODE) == HAL_OSPI_DATA_1_LINE) || \
924 ((MODE) == HAL_OSPI_DATA_2_LINES) || \
925 ((MODE) == HAL_OSPI_DATA_4_LINES) || \
926 ((MODE) == HAL_OSPI_DATA_8_LINES))
930 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ argument
931 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
935 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ argument
936 ((MODE) == HAL_OSPI_DQS_ENABLE))
938 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ argument
939 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
945 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ argument
946 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
948 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ argument
949 ((MODE) == HAL_OSPI_FIXED_LATENCY))
954 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ argument
955 ((MODE) == HAL_OSPI_MATCH_MODE_OR))
957 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ argument
958 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
964 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ argument
965 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
971 #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ argument
972 ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))