Lines Matching refs:Timing
400 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
406 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
407 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
409 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Timing_Init()
411 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
412 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
413 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
414 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
415 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
421 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
422 (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
423 (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | in FMC_NORSRAM_Timing_Init()
424 (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) | in FMC_NORSRAM_Timing_Init()
425 (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | in FMC_NORSRAM_Timing_Init()
426 ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | in FMC_NORSRAM_Timing_Init()
427 ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | in FMC_NORSRAM_Timing_Init()
428 Timing->AccessMode; in FMC_NORSRAM_Timing_Init()
431 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
432 (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
433 (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | in FMC_NORSRAM_Timing_Init()
434 (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | in FMC_NORSRAM_Timing_Init()
435 ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | in FMC_NORSRAM_Timing_Init()
436 ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | in FMC_NORSRAM_Timing_Init()
437 Timing->AccessMode; in FMC_NORSRAM_Timing_Init()
444 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
464 … const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, in FMC_NORSRAM_Extended_Timing_Init() argument
475 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
476 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Extended_Timing_Init()
477 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
479 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Extended_Timing_Init()
481 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Extended_Timing_Init()
482 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Extended_Timing_Init()
487 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
488 … ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
489 … ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
490 … ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
491 … Timing->AccessMode | in FMC_NORSRAM_Extended_Timing_Init()
492 … ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); in FMC_NORSRAM_Extended_Timing_Init()
494 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
495 … ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
496 … ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
497 … Timing->AccessMode | in FMC_NORSRAM_Extended_Timing_Init()
498 … ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); in FMC_NORSRAM_Extended_Timing_Init()
656 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_CommonSpace_Timing_Init() argument
660 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
661 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
662 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
663 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
670 Device->PMEM = (Timing->SetupTime | in FMC_NAND_CommonSpace_Timing_Init()
671 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
672 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
673 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); in FMC_NAND_CommonSpace_Timing_Init()
687 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_AttributeSpace_Timing_Init() argument
691 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
692 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
693 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
694 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
701 Device->PATT = (Timing->SetupTime | in FMC_NAND_AttributeSpace_Timing_Init()
702 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
703 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
704 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); in FMC_NAND_AttributeSpace_Timing_Init()