191 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Init()  argument
199   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Init()
225   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);  in FMC_NORSRAM_Init()
282   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);  in FMC_NORSRAM_Init()
287     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);  in FMC_NORSRAM_Init()
294     SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));  in FMC_NORSRAM_Init()
306     MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime));  in FMC_NORSRAM_Init()
312         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);  in FMC_NORSRAM_Init()
316         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);  in FMC_NORSRAM_Init()
320         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);  in FMC_NORSRAM_Init()
324         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);  in FMC_NORSRAM_Init()
340 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_DeInit()  argument
344   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_DeInit()
349   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
355     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
360     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
363   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
371       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);  in FMC_NORSRAM_DeInit()
375       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);  in FMC_NORSRAM_DeInit()
379       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);  in FMC_NORSRAM_DeInit()
383       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);  in FMC_NORSRAM_DeInit()
399 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Timing_Init()  argument
405   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Timing_Init()
420   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
430   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
441   if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))  in FMC_NORSRAM_Timing_Init()
443     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));  in FMC_NORSRAM_Timing_Init()
445     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);  in FMC_NORSRAM_Timing_Init()
463 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,  in FMC_NORSRAM_Extended_Timing_Init()  argument
474     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));  in FMC_NORSRAM_Extended_Timing_Init()
487 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
494 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
503     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
533 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
536   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Enable()
540   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
551 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
554   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Disable()
558   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
623 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init)  in FMC_NAND_Init()  argument
626   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_Init()
636   MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                            |  in FMC_NAND_Init()
655 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_CommonSpace_Timing_Init()  argument
659   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_CommonSpace_Timing_Init()
670   Device->PMEM = (Timing->SetupTime |  in FMC_NAND_CommonSpace_Timing_Init()
686 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_AttributeSpace_Timing_Init()  argument
690   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_AttributeSpace_Timing_Init()
701   Device->PATT = (Timing->SetupTime |  in FMC_NAND_AttributeSpace_Timing_Init()
715 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
718   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_DeInit()
722   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
729   WRITE_REG(Device->PCR,  0x00000018U);  in FMC_NAND_DeInit()
730   WRITE_REG(Device->SR,   0x00000040U);  in FMC_NAND_DeInit()
731   WRITE_REG(Device->PMEM, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
732   WRITE_REG(Device->PATT, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
763 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
766   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Enable()
773   SET_BIT(Device->PCR, FMC_PCR_ECCEN);  in FMC_NAND_ECC_Enable()
785 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
788   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Disable()
795   CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);  in FMC_NAND_ECC_Disable()
808 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
814   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_GetECC()
821   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
837   *ECCval = (uint32_t)Device->ECCR;  in FMC_NAND_GetECC()