Lines Matching refs:hqspi
260 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, F…
261 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod…
291 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Init() argument
297 if(hqspi == NULL) in HAL_QSPI_Init()
303 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance)); in HAL_QSPI_Init()
304 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler)); in HAL_QSPI_Init()
305 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
306 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting)); in HAL_QSPI_Init()
307 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); in HAL_QSPI_Init()
308 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); in HAL_QSPI_Init()
309 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); in HAL_QSPI_Init()
311 assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); in HAL_QSPI_Init()
313 if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) in HAL_QSPI_Init()
315 assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); in HAL_QSPI_Init()
319 if(hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_Init()
322 hqspi->Lock = HAL_UNLOCKED; in HAL_QSPI_Init()
326 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_Init()
327 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_Init()
328 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_Init()
329 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_Init()
330 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_Init()
331 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_Init()
332 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_Init()
333 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_Init()
334 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_Init()
335 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_Init()
337 if(hqspi->MspInitCallback == NULL) in HAL_QSPI_Init()
339 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_Init()
343 hqspi->MspInitCallback(hqspi); in HAL_QSPI_Init()
346 HAL_QSPI_MspInit(hqspi); in HAL_QSPI_Init()
350 HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); in HAL_QSPI_Init()
354 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_Init()
355 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
358 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Init()
364 …MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUAD… in HAL_QSPI_Init()
365 ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | in HAL_QSPI_Init()
366 hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); in HAL_QSPI_Init()
368 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT), in HAL_QSPI_Init()
369 ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | in HAL_QSPI_Init()
370 hqspi->Init.SampleShifting)); in HAL_QSPI_Init()
374 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), in HAL_QSPI_Init()
375 ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | in HAL_QSPI_Init()
376 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); in HAL_QSPI_Init()
379 __HAL_QSPI_ENABLE(hqspi); in HAL_QSPI_Init()
382 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Init()
385 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Init()
389 __HAL_UNLOCK(hqspi); in HAL_QSPI_Init()
400 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_DeInit() argument
403 if(hqspi == NULL) in HAL_QSPI_DeInit()
409 __HAL_QSPI_DISABLE(hqspi); in HAL_QSPI_DeInit()
412 if(hqspi->MspDeInitCallback == NULL) in HAL_QSPI_DeInit()
414 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_DeInit()
418 hqspi->MspDeInitCallback(hqspi); in HAL_QSPI_DeInit()
421 HAL_QSPI_MspDeInit(hqspi); in HAL_QSPI_DeInit()
425 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_DeInit()
428 hqspi->State = HAL_QSPI_STATE_RESET; in HAL_QSPI_DeInit()
431 __HAL_UNLOCK(hqspi); in HAL_QSPI_DeInit()
441 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspInit() argument
444 UNUSED(hqspi); in HAL_QSPI_MspInit()
456 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspDeInit() argument
459 UNUSED(hqspi); in HAL_QSPI_MspDeInit()
495 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_IRQHandler() argument
498 uint32_t flag = READ_REG(hqspi->Instance->SR); in HAL_QSPI_IRQHandler()
499 uint32_t itsource = READ_REG(hqspi->Instance->CR); in HAL_QSPI_IRQHandler()
504 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
506 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
509 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
511 if (hqspi->TxXferCount > 0U) in HAL_QSPI_IRQHandler()
514 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_IRQHandler()
515 hqspi->pTxBuffPtr++; in HAL_QSPI_IRQHandler()
516 hqspi->TxXferCount--; in HAL_QSPI_IRQHandler()
522 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
527 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
530 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
532 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
535 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
536 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
537 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
543 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
555 hqspi->FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
557 HAL_QSPI_FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
565 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); in HAL_QSPI_IRQHandler()
568 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
571 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
573 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
576 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
579 __HAL_DMA_DISABLE(hqspi->hdma); in HAL_QSPI_IRQHandler()
584 (void)HAL_QSPI_Abort_IT(hqspi); in HAL_QSPI_IRQHandler()
588 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
592 hqspi->TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
594 HAL_QSPI_TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
597 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
599 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
602 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
605 __HAL_DMA_DISABLE(hqspi->hdma); in HAL_QSPI_IRQHandler()
609 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
610 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) in HAL_QSPI_IRQHandler()
612 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
615 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
616 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
617 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
629 (void)HAL_QSPI_Abort_IT(hqspi); in HAL_QSPI_IRQHandler()
633 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
637 hqspi->RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
639 HAL_QSPI_RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
642 else if(hqspi->State == HAL_QSPI_STATE_BUSY) in HAL_QSPI_IRQHandler()
645 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
649 hqspi->CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
651 HAL_QSPI_CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
654 else if(hqspi->State == HAL_QSPI_STATE_ABORT) in HAL_QSPI_IRQHandler()
657 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_IRQHandler()
660 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
662 if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE) in HAL_QSPI_IRQHandler()
668 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
670 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
679 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
681 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
695 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); in HAL_QSPI_IRQHandler()
698 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) in HAL_QSPI_IRQHandler()
701 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_IRQHandler()
704 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
709 hqspi->StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
711 HAL_QSPI_StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
719 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); in HAL_QSPI_IRQHandler()
722 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
725 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; in HAL_QSPI_IRQHandler()
727 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
730 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
733 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_IRQHandler()
734 if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) in HAL_QSPI_IRQHandler()
737 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_IRQHandler()
740 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
744 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
746 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
753 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
757 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
759 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
768 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); in HAL_QSPI_IRQHandler()
772 hqspi->TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
774 HAL_QSPI_TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
792 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Ti… in HAL_QSPI_Command() argument
824 __HAL_LOCK(hqspi); in HAL_QSPI_Command()
826 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command()
828 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command()
831 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command()
834 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_Command()
839 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command()
845 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Command()
849 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Command()
852 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
858 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
868 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command()
881 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) in HAL_QSPI_Command_IT() argument
913 __HAL_LOCK(hqspi); in HAL_QSPI_Command_IT()
915 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command_IT()
917 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command_IT()
920 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command_IT()
923 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Command_IT()
930 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Command_IT()
934 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command_IT()
941 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
944 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); in HAL_QSPI_Command_IT()
949 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command_IT()
952 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
958 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
966 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
981 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Transmit() argument
985 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Transmit()
988 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit()
990 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit()
992 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit()
997 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit()
1000 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
1001 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
1002 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit()
1005 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit()
1007 while(hqspi->TxXferCount > 0U) in HAL_QSPI_Transmit()
1010 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
1017 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_Transmit()
1018 hqspi->pTxBuffPtr++; in HAL_QSPI_Transmit()
1019 hqspi->TxXferCount--; in HAL_QSPI_Transmit()
1025 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
1030 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Transmit()
1034 status = HAL_QSPI_Abort(hqspi); in HAL_QSPI_Transmit()
1040 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit()
1044 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit()
1054 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit()
1068 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Receive() argument
1072 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive()
1073 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Receive()
1076 __HAL_LOCK(hqspi); in HAL_QSPI_Receive()
1078 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive()
1080 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive()
1085 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive()
1088 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1089 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1090 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive()
1093 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive()
1096 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive()
1098 while(hqspi->RxXferCount > 0U) in HAL_QSPI_Receive()
1101 …status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Time… in HAL_QSPI_Receive()
1108 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_Receive()
1109 hqspi->pRxBuffPtr++; in HAL_QSPI_Receive()
1110 hqspi->RxXferCount--; in HAL_QSPI_Receive()
1116 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Receive()
1121 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Receive()
1125 status = HAL_QSPI_Abort(hqspi); in HAL_QSPI_Receive()
1131 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive()
1135 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive()
1145 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive()
1157 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_IT() argument
1162 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_IT()
1164 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_IT()
1166 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_IT()
1171 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_IT()
1174 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1175 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1176 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_IT()
1179 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Transmit_IT()
1182 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_IT()
1185 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1188 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Transmit_IT()
1192 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_IT()
1196 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1204 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1217 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_IT() argument
1220 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_IT()
1223 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_IT()
1225 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_IT()
1227 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_IT()
1232 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_IT()
1235 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1236 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1237 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_IT()
1240 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Receive_IT()
1243 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_IT()
1246 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_IT()
1249 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1252 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Receive_IT()
1256 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_IT()
1260 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1268 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1285 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_DMA() argument
1288 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Transmit_DMA()
1291 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1293 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_DMA()
1296 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_DMA()
1301 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) in HAL_QSPI_Transmit_DMA()
1303 hqspi->TxXferCount = data_size; in HAL_QSPI_Transmit_DMA()
1305 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) in HAL_QSPI_Transmit_DMA()
1307 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Transmit_DMA()
1311 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1315 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1319 hqspi->TxXferCount = (data_size >> 1U); in HAL_QSPI_Transmit_DMA()
1322 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) in HAL_QSPI_Transmit_DMA()
1324 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Transmit_DMA()
1328 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1332 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1336 hqspi->TxXferCount = (data_size >> 2U); in HAL_QSPI_Transmit_DMA()
1347 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_DMA()
1350 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Transmit_DMA()
1353 hqspi->TxXferSize = hqspi->TxXferCount; in HAL_QSPI_Transmit_DMA()
1354 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_DMA()
1357 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_DMA()
1360 hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; in HAL_QSPI_Transmit_DMA()
1363 hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; in HAL_QSPI_Transmit_DMA()
1366 hqspi->hdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Transmit_DMA()
1369 hqspi->hdma->XferAbortCallback = NULL; in HAL_QSPI_Transmit_DMA()
1372 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; in HAL_QSPI_Transmit_DMA()
1373 MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Transmit_DMA()
1376 …if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSi… in HAL_QSPI_Transmit_DMA()
1379 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1382 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Transmit_DMA()
1385 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Transmit_DMA()
1390 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Transmit_DMA()
1391 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit_DMA()
1394 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1400 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1404 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1412 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1429 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_DMA() argument
1432 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_DMA()
1433 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Receive_DMA()
1436 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_DMA()
1438 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_DMA()
1441 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_DMA()
1446 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) in HAL_QSPI_Receive_DMA()
1448 hqspi->RxXferCount = data_size; in HAL_QSPI_Receive_DMA()
1450 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) in HAL_QSPI_Receive_DMA()
1452 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Receive_DMA()
1456 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1460 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1464 hqspi->RxXferCount = (data_size >> 1U); in HAL_QSPI_Receive_DMA()
1467 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) in HAL_QSPI_Receive_DMA()
1469 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Receive_DMA()
1473 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1477 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1481 hqspi->RxXferCount = (data_size >> 2U); in HAL_QSPI_Receive_DMA()
1492 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_DMA()
1495 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Receive_DMA()
1498 hqspi->RxXferSize = hqspi->RxXferCount; in HAL_QSPI_Receive_DMA()
1499 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_DMA()
1502 hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; in HAL_QSPI_Receive_DMA()
1505 hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; in HAL_QSPI_Receive_DMA()
1508 hqspi->hdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Receive_DMA()
1511 hqspi->hdma->XferAbortCallback = NULL; in HAL_QSPI_Receive_DMA()
1514 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; in HAL_QSPI_Receive_DMA()
1515 MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Receive_DMA()
1518 …if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSi… in HAL_QSPI_Receive_DMA()
1521 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_DMA()
1524 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_DMA()
1527 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1530 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Receive_DMA()
1533 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Receive_DMA()
1538 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Receive_DMA()
1539 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive_DMA()
1542 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1548 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1552 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1560 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1575 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_Au… in HAL_QSPI_AutoPolling() argument
1611 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling()
1613 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling()
1615 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling()
1618 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling()
1621 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1626 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling()
1629 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling()
1632 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling()
1636 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling()
1641 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling()
1644 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1648 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); in HAL_QSPI_AutoPolling()
1651 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_AutoPolling()
1661 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling()
1675 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI… in HAL_QSPI_AutoPolling_IT() argument
1712 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1714 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling_IT()
1716 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling_IT()
1719 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling_IT()
1722 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_AutoPolling_IT()
1727 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling_IT()
1730 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling_IT()
1733 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling_IT()
1736 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling_IT()
1740 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); in HAL_QSPI_AutoPolling_IT()
1744 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling_IT()
1747 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1750 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_AutoPolling_IT()
1756 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1764 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1779 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_M… in HAL_QSPI_MemoryMapped() argument
1813 __HAL_LOCK(hqspi); in HAL_QSPI_MemoryMapped()
1815 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_MemoryMapped()
1817 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_MemoryMapped()
1820 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; in HAL_QSPI_MemoryMapped()
1823 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_MemoryMapped()
1828 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); in HAL_QSPI_MemoryMapped()
1835 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); in HAL_QSPI_MemoryMapped()
1838 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); in HAL_QSPI_MemoryMapped()
1841 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); in HAL_QSPI_MemoryMapped()
1845 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); in HAL_QSPI_MemoryMapped()
1854 __HAL_UNLOCK(hqspi); in HAL_QSPI_MemoryMapped()
1865 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_ErrorCallback() argument
1868 UNUSED(hqspi); in HAL_QSPI_ErrorCallback()
1880 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_AbortCpltCallback() argument
1883 UNUSED(hqspi); in HAL_QSPI_AbortCpltCallback()
1895 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_CmdCpltCallback() argument
1898 UNUSED(hqspi); in HAL_QSPI_CmdCpltCallback()
1910 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxCpltCallback() argument
1913 UNUSED(hqspi); in HAL_QSPI_RxCpltCallback()
1925 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxCpltCallback() argument
1928 UNUSED(hqspi); in HAL_QSPI_TxCpltCallback()
1940 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxHalfCpltCallback() argument
1943 UNUSED(hqspi); in HAL_QSPI_RxHalfCpltCallback()
1955 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxHalfCpltCallback() argument
1958 UNUSED(hqspi); in HAL_QSPI_TxHalfCpltCallback()
1970 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_FifoThresholdCallback() argument
1973 UNUSED(hqspi); in HAL_QSPI_FifoThresholdCallback()
1985 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_StatusMatchCallback() argument
1988 UNUSED(hqspi); in HAL_QSPI_StatusMatchCallback()
2000 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TimeOutCallback() argument
2003 UNUSED(hqspi); in HAL_QSPI_TimeOutCallback()
2031 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef … in HAL_QSPI_RegisterCallback() argument
2038 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2043 __HAL_LOCK(hqspi); in HAL_QSPI_RegisterCallback()
2045 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_RegisterCallback()
2050 hqspi->ErrorCallback = pCallback; in HAL_QSPI_RegisterCallback()
2053 hqspi->AbortCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2056 hqspi->FifoThresholdCallback = pCallback; in HAL_QSPI_RegisterCallback()
2059 hqspi->CmdCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2062 hqspi->RxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2065 hqspi->TxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2068 hqspi->RxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2071 hqspi->TxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2074 hqspi->StatusMatchCallback = pCallback; in HAL_QSPI_RegisterCallback()
2077 hqspi->TimeOutCallback = pCallback; in HAL_QSPI_RegisterCallback()
2080 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2083 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2087 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2093 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_RegisterCallback()
2098 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2101 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2105 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2114 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2120 __HAL_UNLOCK(hqspi); in HAL_QSPI_RegisterCallback()
2144 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDe… in HAL_QSPI_UnRegisterCallback() argument
2149 __HAL_LOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2151 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_UnRegisterCallback()
2156 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_UnRegisterCallback()
2159 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_UnRegisterCallback()
2162 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_UnRegisterCallback()
2165 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_UnRegisterCallback()
2168 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2171 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2174 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2177 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2180 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_UnRegisterCallback()
2183 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_UnRegisterCallback()
2186 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2189 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2193 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2199 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_UnRegisterCallback()
2204 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2207 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2211 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2220 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2226 __HAL_UNLOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2258 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetState() argument
2261 return hqspi->State; in HAL_QSPI_GetState()
2269 uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetError() argument
2271 return hqspi->ErrorCode; in HAL_QSPI_GetError()
2279 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort() argument
2285 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort()
2288 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort()
2290 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort()
2293 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort()
2296 status = HAL_DMA_Abort(hqspi->hdma); in HAL_QSPI_Abort()
2299 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Abort()
2303 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort()
2306 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort()
2309 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2313 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort()
2316 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2322 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_Abort()
2325 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2331 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2343 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort_IT() argument
2348 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort_IT()
2351 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort_IT()
2354 hqspi->State = HAL_QSPI_STATE_ABORT; in HAL_QSPI_Abort_IT()
2357 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); in HAL_QSPI_Abort_IT()
2359 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort_IT()
2362 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort_IT()
2365 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_Abort_IT()
2366 if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) in HAL_QSPI_Abort_IT()
2369 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2373 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2375 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2381 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort_IT()
2384 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort_IT()
2387 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in HAL_QSPI_Abort_IT()
2390 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort_IT()
2395 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2407 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) in HAL_QSPI_SetTimeout() argument
2409 hqspi->Timeout = Timeout; in HAL_QSPI_SetTimeout()
2417 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) in HAL_QSPI_SetFifoThreshold() argument
2422 __HAL_LOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2424 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_SetFifoThreshold()
2427 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2430 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_SetFifoThreshold()
2431 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
2439 __HAL_UNLOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2449 uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetFifoThreshold() argument
2451 return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); in HAL_QSPI_GetFifoThreshold()
2462 HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) in HAL_QSPI_SetFlashID() argument
2470 __HAL_LOCK(hqspi); in HAL_QSPI_SetFlashID()
2472 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_SetFlashID()
2475 hqspi->Init.FlashID = FlashID; in HAL_QSPI_SetFlashID()
2478 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); in HAL_QSPI_SetFlashID()
2486 __HAL_UNLOCK(hqspi); in HAL_QSPI_SetFlashID()
2512 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMARxCplt() local
2513 hqspi->RxXferCount = 0U; in QSPI_DMARxCplt()
2516 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMARxCplt()
2526 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMATxCplt() local
2527 hqspi->TxXferCount = 0U; in QSPI_DMATxCplt()
2530 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMATxCplt()
2540 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMARxHalfCplt() local
2543 hqspi->RxHalfCpltCallback(hqspi); in QSPI_DMARxHalfCplt()
2545 HAL_QSPI_RxHalfCpltCallback(hqspi); in QSPI_DMARxHalfCplt()
2556 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMATxHalfCplt() local
2559 hqspi->TxHalfCpltCallback(hqspi); in QSPI_DMATxHalfCplt()
2561 HAL_QSPI_TxHalfCpltCallback(hqspi); in QSPI_DMATxHalfCplt()
2572 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); in QSPI_DMAError() local
2574 hqspi->RxXferCount = 0U; in QSPI_DMAError()
2575 hqspi->TxXferCount = 0U; in QSPI_DMAError()
2576 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in QSPI_DMAError()
2579 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in QSPI_DMAError()
2582 (void)HAL_QSPI_Abort_IT(hqspi); in QSPI_DMAError()
2593 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); in QSPI_DMAAbortCplt() local
2595 hqspi->RxXferCount = 0U; in QSPI_DMAAbortCplt()
2596 hqspi->TxXferCount = 0U; in QSPI_DMAAbortCplt()
2598 if(hqspi->State == HAL_QSPI_STATE_ABORT) in QSPI_DMAAbortCplt()
2602 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in QSPI_DMAAbortCplt()
2605 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMAAbortCplt()
2608 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in QSPI_DMAAbortCplt()
2614 hqspi->State = HAL_QSPI_STATE_READY; in QSPI_DMAAbortCplt()
2618 hqspi->ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2620 HAL_QSPI_ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2634 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, in QSPI_WaitFlagStateUntilTimeout() argument
2638 while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) in QSPI_WaitFlagStateUntilTimeout()
2645 hqspi->State = HAL_QSPI_STATE_ERROR; in QSPI_WaitFlagStateUntilTimeout()
2646 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; in QSPI_WaitFlagStateUntilTimeout()
2667 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod… in QSPI_Config() argument
2674 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); in QSPI_Config()
2682 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2688 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2697 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2704 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2711 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()
2720 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2728 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2735 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2741 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()
2750 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2756 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2765 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2772 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2778 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()
2787 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2795 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2804 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2810 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()