Lines Matching full:mode
54 …uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to acces…
55 … quad mode on two different devices to increase the throughput.
139 used for memory-mapped mode).
146 uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
150 uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase.
154 uint32_t AddressMode; /*!< It indicates the mode of the address.
158 uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase.
162 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
166 …uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes ph…
168 uint32_t DataMode; /*!< It indicates the mode of the data.
171 This field is only used for indirect mode.
173 uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase.
179 uint32_t SIOOMode; /*!< It enables or not the SIOO mode.
194 uint32_t LatencyMode; /*!< It configures the latency mode.
210 This field is only used for indirect mode.
212 … In case of autopolling mode, this parameter can be any value between 1 and 4 */
218 * @brief HAL OSPI Auto Polling mode configuration structure definition
235 * @brief HAL OSPI Memory Mapped mode configuration structure definition
306 … ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configur…
341 … ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */
342 … ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */
350 … ((uint32_t)0x00000000U) /*!< Micron mode */
351 … ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */
353 … ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */
355 …AM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */
356 … ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
370 /** @defgroup OSPI_ClockMode OSPI Clock Mode
409 … /*!< Common configuration (indirect or auto-polling mode) */
410 … /*!< Read configuration (memory-mapped mode) */
411 … /*!< Write configuration (memory-mapped mode) */
425 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode
448 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode
451 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for instru…
452 … ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruc…
457 /** @defgroup OSPI_AddressMode OSPI Address Mode
480 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode
483 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for addres…
484 … ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address…
489 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode
512 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode
515 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for altern…
516 … ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alterna…
521 /** @defgroup OSPI_DataMode OSPI Data Mode
533 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode
536 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for data p…
537 … ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data ph…
542 /** @defgroup OSPI_DQSMode OSPI DQS Mode
551 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode
569 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode
581 … ((uint32_t)0x00000000U) /*!< HyperBus memory mode */
582 … ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
587 /** @defgroup OSPI_MatchMode OSPI Match Mode
590 …t32_t)0x00000000U) /*!< AND match mode between unmasked bi…
591 …nt32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bi…
618 … /*!< Timeout flag: timeout occurs in memory-mapped mode …
619 … /*!< Status match flag: received data matches in autopolling mode …
796 /* OSPI indirect mode functions */
804 /* OSPI status flag polling mode functions */
808 /* OSPI memory-mapped mode functions */
816 /* OSPI indirect mode functions */
823 /* OSPI status flag polling mode functions */
826 /* OSPI memory-mapped mode functions */
876 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ argument
877 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
899 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ argument
900 ((MODE) == HAL_OSPI_CLOCK_MODE_3))
917 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ argument
918 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \
919 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \
920 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \
921 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))
928 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ argument
929 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
931 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ argument
932 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \
933 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \
934 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \
935 ((MODE) == HAL_OSPI_ADDRESS_8_LINES))
942 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ argument
943 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))
945 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ argument
946 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \
947 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \
948 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \
949 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))
956 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ argument
957 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))
959 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ argument
960 ((MODE) == HAL_OSPI_DATA_1_LINE) || \
961 ((MODE) == HAL_OSPI_DATA_2_LINES) || \
962 ((MODE) == HAL_OSPI_DATA_4_LINES) || \
963 ((MODE) == HAL_OSPI_DATA_8_LINES))
967 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ argument
968 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
972 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ argument
973 ((MODE) == HAL_OSPI_DQS_ENABLE))
975 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ argument
976 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
982 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ argument
983 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
985 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ argument
986 ((MODE) == HAL_OSPI_FIXED_LATENCY))
991 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ argument
992 ((MODE) == HAL_OSPI_MATCH_MODE_OR))
994 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ argument
995 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
1001 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ argument
1002 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
1008 #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ argument
1009 ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))