425   uint32_t tmpccer;  in LL_TIM_ENCODER_Init()  local
446   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
461   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_ENCODER_Init()
462   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);  in LL_TIM_ENCODER_Init()
463   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);  in LL_TIM_ENCODER_Init()
464   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
473   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
501   uint32_t tmpccer;  in OC1Config()  local
514   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
529   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);  in OC1Config()
532   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);  in OC1Config()
544   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
560   uint32_t tmpccer;  in OC2Config()  local
573   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
588   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);  in OC2Config()
591   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);  in OC2Config()
603   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
619   uint32_t tmpccer;  in OC3Config()  local
632   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
647   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);  in OC3Config()
650   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);  in OC3Config()
662   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
678   uint32_t tmpccer;  in OC4Config()  local
691   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
706   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);  in OC4Config()
709   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);  in OC4Config()
721   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()