Lines Matching refs:CFGR
251 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); in HAL_RCC_DeInit()
254 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) in HAL_RCC_DeInit()
290 CLEAR_REG(RCC->CFGR); in HAL_RCC_DeInit()
505 >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; in HAL_RCC_OscConfig()
757 pll_config = RCC->CFGR; in HAL_RCC_OscConfig()
832 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
940 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); in HAL_RCC_ClockConfig()
947 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); in HAL_RCC_ClockConfig()
951 …SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFG… in HAL_RCC_ClockConfig()
1085 tmpreg = RCC->CFGR; in HAL_RCC_GetSysClockFreq()
1151 …return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]… in HAL_RCC_GetPCLK1Freq()
1163 …return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); in HAL_RCC_GetPCLK2Freq()
1256 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); in HAL_RCC_GetOscConfig()
1257 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); in HAL_RCC_GetOscConfig()
1258 RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV); in HAL_RCC_GetOscConfig()
1279 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); in HAL_RCC_GetClockConfig()
1282 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); in HAL_RCC_GetClockConfig()
1285 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); in HAL_RCC_GetClockConfig()
1288 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); in HAL_RCC_GetClockConfig()
1347 if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) in RCC_SetFlashLatencyFromMSIRange()