Lines Matching refs:RI
620 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
621 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
622 MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
640 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
641 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
642 MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
660 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
661 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
662 MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
680 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
681 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \
682 MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \
705 #define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM)
707 #define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)
718 SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
722 SET_BIT(RI->ASCR2, (__IOSWITCH__)); \
729 CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
733 CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \
771 CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \
775 SET_BIT(RI->HYSCR1, (__IOPIN__)); \
789 CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
793 SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
807 CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \
811 SET_BIT(RI->HYSCR2, (__IOPIN__)); \
825 CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
829 SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
845 CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \
849 SET_BIT(RI->HYSCR3, (__IOPIN__)); \
867 CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
871 SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
885 CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \
889 SET_BIT(RI->HYSCR4, (__IOPIN__)); \