227 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
269 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)  in HAL_TIM_Base_Init()  argument
272   if (htim == NULL)  in HAL_TIM_Base_Init()
278   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_Base_Init()
279   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));  in HAL_TIM_Base_Init()
280   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));  in HAL_TIM_Base_Init()
281   assert_param(IS_TIM_PERIOD(htim->Init.Period));  in HAL_TIM_Base_Init()
282   assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));  in HAL_TIM_Base_Init()
283   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));  in HAL_TIM_Base_Init()
285   if (htim->State == HAL_TIM_STATE_RESET)  in HAL_TIM_Base_Init()
288     htim->Lock = HAL_UNLOCKED;  in HAL_TIM_Base_Init()
292     TIM_ResetCallback(htim);  in HAL_TIM_Base_Init()
294     if (htim->Base_MspInitCallback == NULL)  in HAL_TIM_Base_Init()
296       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;  in HAL_TIM_Base_Init()
299     htim->Base_MspInitCallback(htim);  in HAL_TIM_Base_Init()
302     HAL_TIM_Base_MspInit(htim);  in HAL_TIM_Base_Init()
307   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_Base_Init()
310   TIM_Base_SetConfig(htim->Instance, &htim->Init);  in HAL_TIM_Base_Init()
313   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;  in HAL_TIM_Base_Init()
316   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Base_Init()
319   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_Base_Init()
329 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_Base_DeInit()  argument
332   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_Base_DeInit()
334   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_Base_DeInit()
337   __HAL_TIM_DISABLE(htim);  in HAL_TIM_Base_DeInit()
340   if (htim->Base_MspDeInitCallback == NULL)  in HAL_TIM_Base_DeInit()
342     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;  in HAL_TIM_Base_DeInit()
345   htim->Base_MspDeInitCallback(htim);  in HAL_TIM_Base_DeInit()
348   HAL_TIM_Base_MspDeInit(htim);  in HAL_TIM_Base_DeInit()
352   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;  in HAL_TIM_Base_DeInit()
355   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);  in HAL_TIM_Base_DeInit()
358   htim->State = HAL_TIM_STATE_RESET;  in HAL_TIM_Base_DeInit()
361   __HAL_UNLOCK(htim);  in HAL_TIM_Base_DeInit()
371 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)  in HAL_TIM_Base_MspInit()  argument
374   UNUSED(htim);  in HAL_TIM_Base_MspInit()
386 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_Base_MspDeInit()  argument
389   UNUSED(htim);  in HAL_TIM_Base_MspDeInit()
402 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)  in HAL_TIM_Base_Start()  argument
407   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_Base_Start()
410   if (htim->State != HAL_TIM_STATE_READY)  in HAL_TIM_Base_Start()
416   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_Base_Start()
419   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_Base_Start()
421     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_Base_Start()
424       __HAL_TIM_ENABLE(htim);  in HAL_TIM_Base_Start()
429     __HAL_TIM_ENABLE(htim);  in HAL_TIM_Base_Start()
441 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)  in HAL_TIM_Base_Stop()  argument
444   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_Base_Stop()
447   __HAL_TIM_DISABLE(htim);  in HAL_TIM_Base_Stop()
450   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_Base_Stop()
461 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)  in HAL_TIM_Base_Start_IT()  argument
466   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_Base_Start_IT()
469   if (htim->State != HAL_TIM_STATE_READY)  in HAL_TIM_Base_Start_IT()
475   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_Base_Start_IT()
478   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);  in HAL_TIM_Base_Start_IT()
481   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_Base_Start_IT()
483     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_Base_Start_IT()
486       __HAL_TIM_ENABLE(htim);  in HAL_TIM_Base_Start_IT()
491     __HAL_TIM_ENABLE(htim);  in HAL_TIM_Base_Start_IT()
503 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)  in HAL_TIM_Base_Stop_IT()  argument
506   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_Base_Stop_IT()
509   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);  in HAL_TIM_Base_Stop_IT()
512   __HAL_TIM_DISABLE(htim);  in HAL_TIM_Base_Stop_IT()
515   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_Base_Stop_IT()
528 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t L…  in HAL_TIM_Base_Start_DMA()  argument
533   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));  in HAL_TIM_Base_Start_DMA()
536   if (htim->State == HAL_TIM_STATE_BUSY)  in HAL_TIM_Base_Start_DMA()
540   else if (htim->State == HAL_TIM_STATE_READY)  in HAL_TIM_Base_Start_DMA()
548       htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_Base_Start_DMA()
557   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;  in HAL_TIM_Base_Start_DMA()
558   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;  in HAL_TIM_Base_Start_DMA()
561   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_Base_Start_DMA()
564 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->AR…  in HAL_TIM_Base_Start_DMA()
572   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);  in HAL_TIM_Base_Start_DMA()
575   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_Base_Start_DMA()
577     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_Base_Start_DMA()
580       __HAL_TIM_ENABLE(htim);  in HAL_TIM_Base_Start_DMA()
585     __HAL_TIM_ENABLE(htim);  in HAL_TIM_Base_Start_DMA()
597 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)  in HAL_TIM_Base_Stop_DMA()  argument
600   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));  in HAL_TIM_Base_Stop_DMA()
603   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);  in HAL_TIM_Base_Stop_DMA()
605   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);  in HAL_TIM_Base_Stop_DMA()
608   __HAL_TIM_DISABLE(htim);  in HAL_TIM_Base_Stop_DMA()
611   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_Base_Stop_DMA()
652 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)  in HAL_TIM_OC_Init()  argument
655   if (htim == NULL)  in HAL_TIM_OC_Init()
661   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_OC_Init()
662   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));  in HAL_TIM_OC_Init()
663   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));  in HAL_TIM_OC_Init()
664   assert_param(IS_TIM_PERIOD(htim->Init.Period));  in HAL_TIM_OC_Init()
665   assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));  in HAL_TIM_OC_Init()
666   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));  in HAL_TIM_OC_Init()
668   if (htim->State == HAL_TIM_STATE_RESET)  in HAL_TIM_OC_Init()
671     htim->Lock = HAL_UNLOCKED;  in HAL_TIM_OC_Init()
675     TIM_ResetCallback(htim);  in HAL_TIM_OC_Init()
677     if (htim->OC_MspInitCallback == NULL)  in HAL_TIM_OC_Init()
679       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;  in HAL_TIM_OC_Init()
682     htim->OC_MspInitCallback(htim);  in HAL_TIM_OC_Init()
685     HAL_TIM_OC_MspInit(htim);  in HAL_TIM_OC_Init()
690   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_OC_Init()
693   TIM_Base_SetConfig(htim->Instance,  &htim->Init);  in HAL_TIM_OC_Init()
696   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;  in HAL_TIM_OC_Init()
699   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_OC_Init()
702   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_OC_Init()
712 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_OC_DeInit()  argument
715   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_OC_DeInit()
717   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_OC_DeInit()
720   __HAL_TIM_DISABLE(htim);  in HAL_TIM_OC_DeInit()
723   if (htim->OC_MspDeInitCallback == NULL)  in HAL_TIM_OC_DeInit()
725     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;  in HAL_TIM_OC_DeInit()
728   htim->OC_MspDeInitCallback(htim);  in HAL_TIM_OC_DeInit()
731   HAL_TIM_OC_MspDeInit(htim);  in HAL_TIM_OC_DeInit()
735   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;  in HAL_TIM_OC_DeInit()
738   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);  in HAL_TIM_OC_DeInit()
741   htim->State = HAL_TIM_STATE_RESET;  in HAL_TIM_OC_DeInit()
744   __HAL_UNLOCK(htim);  in HAL_TIM_OC_DeInit()
754 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)  in HAL_TIM_OC_MspInit()  argument
757   UNUSED(htim);  in HAL_TIM_OC_MspInit()
769 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_OC_MspDeInit()  argument
772   UNUSED(htim);  in HAL_TIM_OC_MspDeInit()
790 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_OC_Start()  argument
795   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_OC_Start()
798   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)  in HAL_TIM_OC_Start()
804   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_OC_Start()
807   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);  in HAL_TIM_OC_Start()
810   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_OC_Start()
812     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_OC_Start()
815       __HAL_TIM_ENABLE(htim);  in HAL_TIM_OC_Start()
820     __HAL_TIM_ENABLE(htim);  in HAL_TIM_OC_Start()
838 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_OC_Stop()  argument
841   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_OC_Stop()
844   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);  in HAL_TIM_OC_Stop()
847   __HAL_TIM_DISABLE(htim);  in HAL_TIM_OC_Stop()
850   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_OC_Stop()
867 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_OC_Start_IT()  argument
873   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_OC_Start_IT()
876   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)  in HAL_TIM_OC_Start_IT()
882   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_OC_Start_IT()
889       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_OC_Start_IT()
896       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_OC_Start_IT()
903       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);  in HAL_TIM_OC_Start_IT()
910       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);  in HAL_TIM_OC_Start_IT()
922     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);  in HAL_TIM_OC_Start_IT()
925     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_OC_Start_IT()
927       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_OC_Start_IT()
930         __HAL_TIM_ENABLE(htim);  in HAL_TIM_OC_Start_IT()
935       __HAL_TIM_ENABLE(htim);  in HAL_TIM_OC_Start_IT()
954 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_OC_Stop_IT()  argument
959   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_OC_Stop_IT()
966       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_OC_Stop_IT()
973       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_OC_Stop_IT()
980       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);  in HAL_TIM_OC_Stop_IT()
987       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);  in HAL_TIM_OC_Stop_IT()
999     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);  in HAL_TIM_OC_Stop_IT()
1002     __HAL_TIM_DISABLE(htim);  in HAL_TIM_OC_Stop_IT()
1005     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_OC_Stop_IT()
1025 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *p…  in HAL_TIM_OC_Start_DMA()  argument
1032   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_OC_Start_DMA()
1035   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)  in HAL_TIM_OC_Start_DMA()
1039   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)  in HAL_TIM_OC_Start_DMA()
1047       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_OC_Start_DMA()
1060       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_OC_Start_DMA()
1061       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_OC_Start_DMA()
1064       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_OC_Start_DMA()
1067 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,  in HAL_TIM_OC_Start_DMA()
1075       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);  in HAL_TIM_OC_Start_DMA()
1082       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_OC_Start_DMA()
1083       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_OC_Start_DMA()
1086       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_OC_Start_DMA()
1089 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,  in HAL_TIM_OC_Start_DMA()
1097       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);  in HAL_TIM_OC_Start_DMA()
1104       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_OC_Start_DMA()
1105       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_OC_Start_DMA()
1108       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_OC_Start_DMA()
1111 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,  in HAL_TIM_OC_Start_DMA()
1118       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);  in HAL_TIM_OC_Start_DMA()
1125       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_OC_Start_DMA()
1126       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_OC_Start_DMA()
1129       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_OC_Start_DMA()
1132 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,  in HAL_TIM_OC_Start_DMA()
1139       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);  in HAL_TIM_OC_Start_DMA()
1151     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);  in HAL_TIM_OC_Start_DMA()
1154     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_OC_Start_DMA()
1156       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_OC_Start_DMA()
1159         __HAL_TIM_ENABLE(htim);  in HAL_TIM_OC_Start_DMA()
1164       __HAL_TIM_ENABLE(htim);  in HAL_TIM_OC_Start_DMA()
1183 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_OC_Stop_DMA()  argument
1188   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_OC_Stop_DMA()
1195       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);  in HAL_TIM_OC_Stop_DMA()
1196       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);  in HAL_TIM_OC_Stop_DMA()
1203       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);  in HAL_TIM_OC_Stop_DMA()
1204       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);  in HAL_TIM_OC_Stop_DMA()
1211       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);  in HAL_TIM_OC_Stop_DMA()
1212       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);  in HAL_TIM_OC_Stop_DMA()
1219       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);  in HAL_TIM_OC_Stop_DMA()
1220       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);  in HAL_TIM_OC_Stop_DMA()
1232     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);  in HAL_TIM_OC_Stop_DMA()
1235     __HAL_TIM_DISABLE(htim);  in HAL_TIM_OC_Stop_DMA()
1238     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_OC_Stop_DMA()
1280 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)  in HAL_TIM_PWM_Init()  argument
1283   if (htim == NULL)  in HAL_TIM_PWM_Init()
1289   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_PWM_Init()
1290   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));  in HAL_TIM_PWM_Init()
1291   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));  in HAL_TIM_PWM_Init()
1292   assert_param(IS_TIM_PERIOD(htim->Init.Period));  in HAL_TIM_PWM_Init()
1293   assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));  in HAL_TIM_PWM_Init()
1294   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));  in HAL_TIM_PWM_Init()
1296   if (htim->State == HAL_TIM_STATE_RESET)  in HAL_TIM_PWM_Init()
1299     htim->Lock = HAL_UNLOCKED;  in HAL_TIM_PWM_Init()
1303     TIM_ResetCallback(htim);  in HAL_TIM_PWM_Init()
1305     if (htim->PWM_MspInitCallback == NULL)  in HAL_TIM_PWM_Init()
1307       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;  in HAL_TIM_PWM_Init()
1310     htim->PWM_MspInitCallback(htim);  in HAL_TIM_PWM_Init()
1313     HAL_TIM_PWM_MspInit(htim);  in HAL_TIM_PWM_Init()
1318   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_PWM_Init()
1321   TIM_Base_SetConfig(htim->Instance, &htim->Init);  in HAL_TIM_PWM_Init()
1324   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;  in HAL_TIM_PWM_Init()
1327   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_PWM_Init()
1330   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_PWM_Init()
1340 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_PWM_DeInit()  argument
1343   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_PWM_DeInit()
1345   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_PWM_DeInit()
1348   __HAL_TIM_DISABLE(htim);  in HAL_TIM_PWM_DeInit()
1351   if (htim->PWM_MspDeInitCallback == NULL)  in HAL_TIM_PWM_DeInit()
1353     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;  in HAL_TIM_PWM_DeInit()
1356   htim->PWM_MspDeInitCallback(htim);  in HAL_TIM_PWM_DeInit()
1359   HAL_TIM_PWM_MspDeInit(htim);  in HAL_TIM_PWM_DeInit()
1363   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;  in HAL_TIM_PWM_DeInit()
1366   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);  in HAL_TIM_PWM_DeInit()
1369   htim->State = HAL_TIM_STATE_RESET;  in HAL_TIM_PWM_DeInit()
1372   __HAL_UNLOCK(htim);  in HAL_TIM_PWM_DeInit()
1382 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)  in HAL_TIM_PWM_MspInit()  argument
1385   UNUSED(htim);  in HAL_TIM_PWM_MspInit()
1397 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_PWM_MspDeInit()  argument
1400   UNUSED(htim);  in HAL_TIM_PWM_MspDeInit()
1418 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_PWM_Start()  argument
1423   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_PWM_Start()
1426   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)  in HAL_TIM_PWM_Start()
1432   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_PWM_Start()
1435   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);  in HAL_TIM_PWM_Start()
1438   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_PWM_Start()
1440     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_PWM_Start()
1443       __HAL_TIM_ENABLE(htim);  in HAL_TIM_PWM_Start()
1448     __HAL_TIM_ENABLE(htim);  in HAL_TIM_PWM_Start()
1466 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_PWM_Stop()  argument
1469   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_PWM_Stop()
1472   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);  in HAL_TIM_PWM_Stop()
1475   __HAL_TIM_DISABLE(htim);  in HAL_TIM_PWM_Stop()
1478   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_PWM_Stop()
1495 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_PWM_Start_IT()  argument
1501   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_PWM_Start_IT()
1504   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)  in HAL_TIM_PWM_Start_IT()
1510   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_PWM_Start_IT()
1517       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_PWM_Start_IT()
1524       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_PWM_Start_IT()
1531       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);  in HAL_TIM_PWM_Start_IT()
1538       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);  in HAL_TIM_PWM_Start_IT()
1550     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);  in HAL_TIM_PWM_Start_IT()
1553     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_PWM_Start_IT()
1555       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_PWM_Start_IT()
1558         __HAL_TIM_ENABLE(htim);  in HAL_TIM_PWM_Start_IT()
1563       __HAL_TIM_ENABLE(htim);  in HAL_TIM_PWM_Start_IT()
1582 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_PWM_Stop_IT()  argument
1587   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_PWM_Stop_IT()
1594       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_PWM_Stop_IT()
1601       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_PWM_Stop_IT()
1608       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);  in HAL_TIM_PWM_Stop_IT()
1615       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);  in HAL_TIM_PWM_Stop_IT()
1627     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);  in HAL_TIM_PWM_Stop_IT()
1630     __HAL_TIM_DISABLE(htim);  in HAL_TIM_PWM_Stop_IT()
1633     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_PWM_Stop_IT()
1653 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *…  in HAL_TIM_PWM_Start_DMA()  argument
1660   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_PWM_Start_DMA()
1663   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)  in HAL_TIM_PWM_Start_DMA()
1667   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)  in HAL_TIM_PWM_Start_DMA()
1675       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_PWM_Start_DMA()
1688       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_PWM_Start_DMA()
1689       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_PWM_Start_DMA()
1692       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_PWM_Start_DMA()
1695 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,  in HAL_TIM_PWM_Start_DMA()
1703       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);  in HAL_TIM_PWM_Start_DMA()
1710       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_PWM_Start_DMA()
1711       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_PWM_Start_DMA()
1714       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_PWM_Start_DMA()
1717 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,  in HAL_TIM_PWM_Start_DMA()
1724       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);  in HAL_TIM_PWM_Start_DMA()
1731       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_PWM_Start_DMA()
1732       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_PWM_Start_DMA()
1735       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_PWM_Start_DMA()
1738 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,  in HAL_TIM_PWM_Start_DMA()
1745       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);  in HAL_TIM_PWM_Start_DMA()
1752       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_PWM_Start_DMA()
1753       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_PWM_Start_DMA()
1756       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_PWM_Start_DMA()
1759 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,  in HAL_TIM_PWM_Start_DMA()
1766       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);  in HAL_TIM_PWM_Start_DMA()
1778     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);  in HAL_TIM_PWM_Start_DMA()
1781     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_PWM_Start_DMA()
1783       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_PWM_Start_DMA()
1786         __HAL_TIM_ENABLE(htim);  in HAL_TIM_PWM_Start_DMA()
1791       __HAL_TIM_ENABLE(htim);  in HAL_TIM_PWM_Start_DMA()
1810 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_PWM_Stop_DMA()  argument
1815   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_PWM_Stop_DMA()
1822       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);  in HAL_TIM_PWM_Stop_DMA()
1823       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);  in HAL_TIM_PWM_Stop_DMA()
1830       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);  in HAL_TIM_PWM_Stop_DMA()
1831       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);  in HAL_TIM_PWM_Stop_DMA()
1838       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);  in HAL_TIM_PWM_Stop_DMA()
1839       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);  in HAL_TIM_PWM_Stop_DMA()
1846       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);  in HAL_TIM_PWM_Stop_DMA()
1847       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);  in HAL_TIM_PWM_Stop_DMA()
1859     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);  in HAL_TIM_PWM_Stop_DMA()
1862     __HAL_TIM_DISABLE(htim);  in HAL_TIM_PWM_Stop_DMA()
1865     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_PWM_Stop_DMA()
1907 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)  in HAL_TIM_IC_Init()  argument
1910   if (htim == NULL)  in HAL_TIM_IC_Init()
1916   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_IC_Init()
1917   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));  in HAL_TIM_IC_Init()
1918   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));  in HAL_TIM_IC_Init()
1919   assert_param(IS_TIM_PERIOD(htim->Init.Period));  in HAL_TIM_IC_Init()
1920   assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));  in HAL_TIM_IC_Init()
1921   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));  in HAL_TIM_IC_Init()
1923   if (htim->State == HAL_TIM_STATE_RESET)  in HAL_TIM_IC_Init()
1926     htim->Lock = HAL_UNLOCKED;  in HAL_TIM_IC_Init()
1930     TIM_ResetCallback(htim);  in HAL_TIM_IC_Init()
1932     if (htim->IC_MspInitCallback == NULL)  in HAL_TIM_IC_Init()
1934       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;  in HAL_TIM_IC_Init()
1937     htim->IC_MspInitCallback(htim);  in HAL_TIM_IC_Init()
1940     HAL_TIM_IC_MspInit(htim);  in HAL_TIM_IC_Init()
1945   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_IC_Init()
1948   TIM_Base_SetConfig(htim->Instance, &htim->Init);  in HAL_TIM_IC_Init()
1951   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;  in HAL_TIM_IC_Init()
1954   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_IC_Init()
1957   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_IC_Init()
1967 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_IC_DeInit()  argument
1970   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_IC_DeInit()
1972   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_IC_DeInit()
1975   __HAL_TIM_DISABLE(htim);  in HAL_TIM_IC_DeInit()
1978   if (htim->IC_MspDeInitCallback == NULL)  in HAL_TIM_IC_DeInit()
1980     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;  in HAL_TIM_IC_DeInit()
1983   htim->IC_MspDeInitCallback(htim);  in HAL_TIM_IC_DeInit()
1986   HAL_TIM_IC_MspDeInit(htim);  in HAL_TIM_IC_DeInit()
1990   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;  in HAL_TIM_IC_DeInit()
1993   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);  in HAL_TIM_IC_DeInit()
1996   htim->State = HAL_TIM_STATE_RESET;  in HAL_TIM_IC_DeInit()
1999   __HAL_UNLOCK(htim);  in HAL_TIM_IC_DeInit()
2009 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)  in HAL_TIM_IC_MspInit()  argument
2012   UNUSED(htim);  in HAL_TIM_IC_MspInit()
2024 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_IC_MspDeInit()  argument
2027   UNUSED(htim);  in HAL_TIM_IC_MspDeInit()
2045 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_IC_Start()  argument
2048   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);  in HAL_TIM_IC_Start()
2051   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_IC_Start()
2060   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_IC_Start()
2063   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);  in HAL_TIM_IC_Start()
2066   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_IC_Start()
2068     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_IC_Start()
2071       __HAL_TIM_ENABLE(htim);  in HAL_TIM_IC_Start()
2076     __HAL_TIM_ENABLE(htim);  in HAL_TIM_IC_Start()
2094 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_IC_Stop()  argument
2097   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_IC_Stop()
2100   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);  in HAL_TIM_IC_Stop()
2103   __HAL_TIM_DISABLE(htim);  in HAL_TIM_IC_Stop()
2106   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_IC_Stop()
2123 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_IC_Start_IT()  argument
2128   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);  in HAL_TIM_IC_Start_IT()
2131   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_IC_Start_IT()
2140   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_IC_Start_IT()
2147       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_IC_Start_IT()
2154       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_IC_Start_IT()
2161       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);  in HAL_TIM_IC_Start_IT()
2168       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);  in HAL_TIM_IC_Start_IT()
2180     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);  in HAL_TIM_IC_Start_IT()
2183     if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_IC_Start_IT()
2185       tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_IC_Start_IT()
2188         __HAL_TIM_ENABLE(htim);  in HAL_TIM_IC_Start_IT()
2193       __HAL_TIM_ENABLE(htim);  in HAL_TIM_IC_Start_IT()
2212 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_IC_Stop_IT()  argument
2217   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_IC_Stop_IT()
2224       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_IC_Stop_IT()
2231       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_IC_Stop_IT()
2238       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);  in HAL_TIM_IC_Stop_IT()
2245       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);  in HAL_TIM_IC_Stop_IT()
2257     TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);  in HAL_TIM_IC_Stop_IT()
2260     __HAL_TIM_DISABLE(htim);  in HAL_TIM_IC_Stop_IT()
2263     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_IC_Stop_IT()
2283 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, …  in HAL_TIM_IC_Start_DMA()  argument
2288   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);  in HAL_TIM_IC_Start_DMA()
2291   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_IC_Start_DMA()
2292   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));  in HAL_TIM_IC_Start_DMA()
2307       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_IC_Start_DMA()
2316   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);  in HAL_TIM_IC_Start_DMA()
2323       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_IC_Start_DMA()
2324       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_IC_Start_DMA()
2327       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_IC_Start_DMA()
2330 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,  in HAL_TIM_IC_Start_DMA()
2337       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);  in HAL_TIM_IC_Start_DMA()
2344       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_IC_Start_DMA()
2345       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_IC_Start_DMA()
2348       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_IC_Start_DMA()
2351 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,  in HAL_TIM_IC_Start_DMA()
2358       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);  in HAL_TIM_IC_Start_DMA()
2365       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_IC_Start_DMA()
2366       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_IC_Start_DMA()
2369       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_IC_Start_DMA()
2372 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,  in HAL_TIM_IC_Start_DMA()
2379       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);  in HAL_TIM_IC_Start_DMA()
2386       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_IC_Start_DMA()
2387       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_IC_Start_DMA()
2390       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_IC_Start_DMA()
2393 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,  in HAL_TIM_IC_Start_DMA()
2400       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);  in HAL_TIM_IC_Start_DMA()
2410   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))  in HAL_TIM_IC_Start_DMA()
2412     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;  in HAL_TIM_IC_Start_DMA()
2415       __HAL_TIM_ENABLE(htim);  in HAL_TIM_IC_Start_DMA()
2420     __HAL_TIM_ENABLE(htim);  in HAL_TIM_IC_Start_DMA()
2438 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_IC_Stop_DMA()  argument
2443   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_IC_Stop_DMA()
2444   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));  in HAL_TIM_IC_Stop_DMA()
2447   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);  in HAL_TIM_IC_Stop_DMA()
2454       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);  in HAL_TIM_IC_Stop_DMA()
2455       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);  in HAL_TIM_IC_Stop_DMA()
2462       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);  in HAL_TIM_IC_Stop_DMA()
2463       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);  in HAL_TIM_IC_Stop_DMA()
2470       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);  in HAL_TIM_IC_Stop_DMA()
2471       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);  in HAL_TIM_IC_Stop_DMA()
2478       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);  in HAL_TIM_IC_Stop_DMA()
2479       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);  in HAL_TIM_IC_Stop_DMA()
2491     __HAL_TIM_DISABLE(htim);  in HAL_TIM_IC_Stop_DMA()
2494     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_IC_Stop_DMA()
2542 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)  in HAL_TIM_OnePulse_Init()  argument
2545   if (htim == NULL)  in HAL_TIM_OnePulse_Init()
2551   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_OnePulse_Init()
2552   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));  in HAL_TIM_OnePulse_Init()
2553   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));  in HAL_TIM_OnePulse_Init()
2555   assert_param(IS_TIM_PERIOD(htim->Init.Period));  in HAL_TIM_OnePulse_Init()
2556   assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));  in HAL_TIM_OnePulse_Init()
2557   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));  in HAL_TIM_OnePulse_Init()
2559   if (htim->State == HAL_TIM_STATE_RESET)  in HAL_TIM_OnePulse_Init()
2562     htim->Lock = HAL_UNLOCKED;  in HAL_TIM_OnePulse_Init()
2566     TIM_ResetCallback(htim);  in HAL_TIM_OnePulse_Init()
2568     if (htim->OnePulse_MspInitCallback == NULL)  in HAL_TIM_OnePulse_Init()
2570       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;  in HAL_TIM_OnePulse_Init()
2573     htim->OnePulse_MspInitCallback(htim);  in HAL_TIM_OnePulse_Init()
2576     HAL_TIM_OnePulse_MspInit(htim);  in HAL_TIM_OnePulse_Init()
2581   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_OnePulse_Init()
2584   TIM_Base_SetConfig(htim->Instance, &htim->Init);  in HAL_TIM_OnePulse_Init()
2587   htim->Instance->CR1 &= ~TIM_CR1_OPM;  in HAL_TIM_OnePulse_Init()
2590   htim->Instance->CR1 |= OnePulseMode;  in HAL_TIM_OnePulse_Init()
2593   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;  in HAL_TIM_OnePulse_Init()
2596   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_OnePulse_Init()
2597   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_OnePulse_Init()
2600   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_OnePulse_Init()
2610 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_OnePulse_DeInit()  argument
2613   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_OnePulse_DeInit()
2615   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_OnePulse_DeInit()
2618   __HAL_TIM_DISABLE(htim);  in HAL_TIM_OnePulse_DeInit()
2621   if (htim->OnePulse_MspDeInitCallback == NULL)  in HAL_TIM_OnePulse_DeInit()
2623     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;  in HAL_TIM_OnePulse_DeInit()
2626   htim->OnePulse_MspDeInitCallback(htim);  in HAL_TIM_OnePulse_DeInit()
2629   HAL_TIM_OnePulse_MspDeInit(htim);  in HAL_TIM_OnePulse_DeInit()
2633   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;  in HAL_TIM_OnePulse_DeInit()
2636   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);  in HAL_TIM_OnePulse_DeInit()
2637   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);  in HAL_TIM_OnePulse_DeInit()
2640   htim->State = HAL_TIM_STATE_RESET;  in HAL_TIM_OnePulse_DeInit()
2643   __HAL_UNLOCK(htim);  in HAL_TIM_OnePulse_DeInit()
2653 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)  in HAL_TIM_OnePulse_MspInit()  argument
2656   UNUSED(htim);  in HAL_TIM_OnePulse_MspInit()
2668 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_OnePulse_MspDeInit()  argument
2671   UNUSED(htim);  in HAL_TIM_OnePulse_MspDeInit()
2688 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)  in HAL_TIM_OnePulse_Start()  argument
2690   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);  in HAL_TIM_OnePulse_Start()
2691   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);  in HAL_TIM_OnePulse_Start()
2704   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_OnePulse_Start()
2705   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_OnePulse_Start()
2716   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  in HAL_TIM_OnePulse_Start()
2717   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);  in HAL_TIM_OnePulse_Start()
2733 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)  in HAL_TIM_OnePulse_Stop()  argument
2744   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);  in HAL_TIM_OnePulse_Stop()
2745   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);  in HAL_TIM_OnePulse_Stop()
2748   __HAL_TIM_DISABLE(htim);  in HAL_TIM_OnePulse_Stop()
2751   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_OnePulse_Stop()
2752   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_OnePulse_Stop()
2768 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)  in HAL_TIM_OnePulse_Start_IT()  argument
2770   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);  in HAL_TIM_OnePulse_Start_IT()
2771   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);  in HAL_TIM_OnePulse_Start_IT()
2784   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_OnePulse_Start_IT()
2785   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_OnePulse_Start_IT()
2797   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_OnePulse_Start_IT()
2800   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_OnePulse_Start_IT()
2802   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  in HAL_TIM_OnePulse_Start_IT()
2803   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);  in HAL_TIM_OnePulse_Start_IT()
2819 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)  in HAL_TIM_OnePulse_Stop_IT()  argument
2825   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_OnePulse_Stop_IT()
2828   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_OnePulse_Stop_IT()
2835   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);  in HAL_TIM_OnePulse_Stop_IT()
2836   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);  in HAL_TIM_OnePulse_Stop_IT()
2839   __HAL_TIM_DISABLE(htim);  in HAL_TIM_OnePulse_Stop_IT()
2842   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_OnePulse_Stop_IT()
2843   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_OnePulse_Stop_IT()
2890 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sCon…  in HAL_TIM_Encoder_Init()  argument
2897   if (htim == NULL)  in HAL_TIM_Encoder_Init()
2903   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));  in HAL_TIM_Encoder_Init()
2904   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));  in HAL_TIM_Encoder_Init()
2905   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));  in HAL_TIM_Encoder_Init()
2906   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));  in HAL_TIM_Encoder_Init()
2916   assert_param(IS_TIM_PERIOD(htim->Init.Period));  in HAL_TIM_Encoder_Init()
2917   assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));  in HAL_TIM_Encoder_Init()
2919   if (htim->State == HAL_TIM_STATE_RESET)  in HAL_TIM_Encoder_Init()
2922     htim->Lock = HAL_UNLOCKED;  in HAL_TIM_Encoder_Init()
2926     TIM_ResetCallback(htim);  in HAL_TIM_Encoder_Init()
2928     if (htim->Encoder_MspInitCallback == NULL)  in HAL_TIM_Encoder_Init()
2930       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;  in HAL_TIM_Encoder_Init()
2933     htim->Encoder_MspInitCallback(htim);  in HAL_TIM_Encoder_Init()
2936     HAL_TIM_Encoder_MspInit(htim);  in HAL_TIM_Encoder_Init()
2941   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_Encoder_Init()
2944   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);  in HAL_TIM_Encoder_Init()
2947   TIM_Base_SetConfig(htim->Instance, &htim->Init);  in HAL_TIM_Encoder_Init()
2950   tmpsmcr = htim->Instance->SMCR;  in HAL_TIM_Encoder_Init()
2953   tmpccmr1 = htim->Instance->CCMR1;  in HAL_TIM_Encoder_Init()
2956   tmpccer = htim->Instance->CCER;  in HAL_TIM_Encoder_Init()
2977   htim->Instance->SMCR = tmpsmcr;  in HAL_TIM_Encoder_Init()
2980   htim->Instance->CCMR1 = tmpccmr1;  in HAL_TIM_Encoder_Init()
2983   htim->Instance->CCER = tmpccer;  in HAL_TIM_Encoder_Init()
2986   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;  in HAL_TIM_Encoder_Init()
2989   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Encoder_Init()
2990   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Encoder_Init()
2993   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_Encoder_Init()
3004 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_Encoder_DeInit()  argument
3007   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_Encoder_DeInit()
3009   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_Encoder_DeInit()
3012   __HAL_TIM_DISABLE(htim);  in HAL_TIM_Encoder_DeInit()
3015   if (htim->Encoder_MspDeInitCallback == NULL)  in HAL_TIM_Encoder_DeInit()
3017     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;  in HAL_TIM_Encoder_DeInit()
3020   htim->Encoder_MspDeInitCallback(htim);  in HAL_TIM_Encoder_DeInit()
3023   HAL_TIM_Encoder_MspDeInit(htim);  in HAL_TIM_Encoder_DeInit()
3027   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;  in HAL_TIM_Encoder_DeInit()
3030   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);  in HAL_TIM_Encoder_DeInit()
3031   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);  in HAL_TIM_Encoder_DeInit()
3034   htim->State = HAL_TIM_STATE_RESET;  in HAL_TIM_Encoder_DeInit()
3037   __HAL_UNLOCK(htim);  in HAL_TIM_Encoder_DeInit()
3047 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)  in HAL_TIM_Encoder_MspInit()  argument
3050   UNUSED(htim);  in HAL_TIM_Encoder_MspInit()
3062 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)  in HAL_TIM_Encoder_MspDeInit()  argument
3065   UNUSED(htim);  in HAL_TIM_Encoder_MspDeInit()
3082 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_Encoder_Start()  argument
3084   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);  in HAL_TIM_Encoder_Start()
3085   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);  in HAL_TIM_Encoder_Start()
3088   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));  in HAL_TIM_Encoder_Start()
3099       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start()
3110       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start()
3122       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start()
3123       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start()
3132       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start()
3138       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start()
3144       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start()
3145       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start()
3150   __HAL_TIM_ENABLE(htim);  in HAL_TIM_Encoder_Start()
3166 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_Encoder_Stop()  argument
3169   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));  in HAL_TIM_Encoder_Stop()
3177       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop()
3183       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop()
3189       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop()
3190       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop()
3196   __HAL_TIM_DISABLE(htim);  in HAL_TIM_Encoder_Stop()
3201     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Encoder_Stop()
3205     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Encoder_Stop()
3206     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Encoder_Stop()
3223 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_Encoder_Start_IT()  argument
3225   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);  in HAL_TIM_Encoder_Start_IT()
3226   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);  in HAL_TIM_Encoder_Start_IT()
3229   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));  in HAL_TIM_Encoder_Start_IT()
3240       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start_IT()
3251       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start_IT()
3263       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start_IT()
3264       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start_IT()
3274       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start_IT()
3275       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_Encoder_Start_IT()
3281       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start_IT()
3282       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_Encoder_Start_IT()
3288       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start_IT()
3289       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start_IT()
3290       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_Encoder_Start_IT()
3291       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_Encoder_Start_IT()
3297   __HAL_TIM_ENABLE(htim);  in HAL_TIM_Encoder_Start_IT()
3313 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_Encoder_Stop_IT()  argument
3316   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));  in HAL_TIM_Encoder_Stop_IT()
3322     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop_IT()
3325     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_Encoder_Stop_IT()
3329     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop_IT()
3332     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_Encoder_Stop_IT()
3336     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop_IT()
3337     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop_IT()
3340     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);  in HAL_TIM_Encoder_Stop_IT()
3341     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);  in HAL_TIM_Encoder_Stop_IT()
3345   __HAL_TIM_DISABLE(htim);  in HAL_TIM_Encoder_Stop_IT()
3350     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Encoder_Stop_IT()
3354     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Encoder_Stop_IT()
3355     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Encoder_Stop_IT()
3375 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pD…  in HAL_TIM_Encoder_Start_DMA()  argument
3378   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);  in HAL_TIM_Encoder_Start_DMA()
3379   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);  in HAL_TIM_Encoder_Start_DMA()
3382   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));  in HAL_TIM_Encoder_Start_DMA()
3399         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start_DMA()
3421         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start_DMA()
3445         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start_DMA()
3446         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);  in HAL_TIM_Encoder_Start_DMA()
3460       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_Encoder_Start_DMA()
3461       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_Encoder_Start_DMA()
3464       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_Encoder_Start_DMA()
3467 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,  in HAL_TIM_Encoder_Start_DMA()
3474       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);  in HAL_TIM_Encoder_Start_DMA()
3477       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start_DMA()
3480       __HAL_TIM_ENABLE(htim);  in HAL_TIM_Encoder_Start_DMA()
3488       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_Encoder_Start_DMA()
3489       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_Encoder_Start_DMA()
3492       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;  in HAL_TIM_Encoder_Start_DMA()
3494 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,  in HAL_TIM_Encoder_Start_DMA()
3501       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);  in HAL_TIM_Encoder_Start_DMA()
3504       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start_DMA()
3507       __HAL_TIM_ENABLE(htim);  in HAL_TIM_Encoder_Start_DMA()
3515       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_Encoder_Start_DMA()
3516       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_Encoder_Start_DMA()
3519       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_Encoder_Start_DMA()
3522 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,  in HAL_TIM_Encoder_Start_DMA()
3530       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_Encoder_Start_DMA()
3531       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_Encoder_Start_DMA()
3534       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_Encoder_Start_DMA()
3537 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,  in HAL_TIM_Encoder_Start_DMA()
3545       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);  in HAL_TIM_Encoder_Start_DMA()
3547       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);  in HAL_TIM_Encoder_Start_DMA()
3550       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start_DMA()
3551       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);  in HAL_TIM_Encoder_Start_DMA()
3554       __HAL_TIM_ENABLE(htim);  in HAL_TIM_Encoder_Start_DMA()
3574 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_Encoder_Stop_DMA()  argument
3577   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));  in HAL_TIM_Encoder_Stop_DMA()
3583     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop_DMA()
3586     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);  in HAL_TIM_Encoder_Stop_DMA()
3587     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);  in HAL_TIM_Encoder_Stop_DMA()
3591     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop_DMA()
3594     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);  in HAL_TIM_Encoder_Stop_DMA()
3595     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);  in HAL_TIM_Encoder_Stop_DMA()
3599     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop_DMA()
3600     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);  in HAL_TIM_Encoder_Stop_DMA()
3603     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);  in HAL_TIM_Encoder_Stop_DMA()
3604     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);  in HAL_TIM_Encoder_Stop_DMA()
3605     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);  in HAL_TIM_Encoder_Stop_DMA()
3606     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);  in HAL_TIM_Encoder_Stop_DMA()
3610   __HAL_TIM_DISABLE(htim);  in HAL_TIM_Encoder_Stop_DMA()
3615     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Encoder_Stop_DMA()
3619     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Encoder_Stop_DMA()
3620     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);  in HAL_TIM_Encoder_Stop_DMA()
3648 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)  in HAL_TIM_IRQHandler()  argument
3651   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)  in HAL_TIM_IRQHandler()
3653     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)  in HAL_TIM_IRQHandler()
3656         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);  in HAL_TIM_IRQHandler()
3657         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;  in HAL_TIM_IRQHandler()
3660         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)  in HAL_TIM_IRQHandler()
3663           htim->IC_CaptureCallback(htim);  in HAL_TIM_IRQHandler()
3665           HAL_TIM_IC_CaptureCallback(htim);  in HAL_TIM_IRQHandler()
3672           htim->OC_DelayElapsedCallback(htim);  in HAL_TIM_IRQHandler()
3673           htim->PWM_PulseFinishedCallback(htim);  in HAL_TIM_IRQHandler()
3675           HAL_TIM_OC_DelayElapsedCallback(htim);  in HAL_TIM_IRQHandler()
3676           HAL_TIM_PWM_PulseFinishedCallback(htim);  in HAL_TIM_IRQHandler()
3679         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;  in HAL_TIM_IRQHandler()
3684   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)  in HAL_TIM_IRQHandler()
3686     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)  in HAL_TIM_IRQHandler()
3688       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);  in HAL_TIM_IRQHandler()
3689       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;  in HAL_TIM_IRQHandler()
3691       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)  in HAL_TIM_IRQHandler()
3694         htim->IC_CaptureCallback(htim);  in HAL_TIM_IRQHandler()
3696         HAL_TIM_IC_CaptureCallback(htim);  in HAL_TIM_IRQHandler()
3703         htim->OC_DelayElapsedCallback(htim);  in HAL_TIM_IRQHandler()
3704         htim->PWM_PulseFinishedCallback(htim);  in HAL_TIM_IRQHandler()
3706         HAL_TIM_OC_DelayElapsedCallback(htim);  in HAL_TIM_IRQHandler()
3707         HAL_TIM_PWM_PulseFinishedCallback(htim);  in HAL_TIM_IRQHandler()
3710       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;  in HAL_TIM_IRQHandler()
3714   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)  in HAL_TIM_IRQHandler()
3716     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)  in HAL_TIM_IRQHandler()
3718       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);  in HAL_TIM_IRQHandler()
3719       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;  in HAL_TIM_IRQHandler()
3721       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)  in HAL_TIM_IRQHandler()
3724         htim->IC_CaptureCallback(htim);  in HAL_TIM_IRQHandler()
3726         HAL_TIM_IC_CaptureCallback(htim);  in HAL_TIM_IRQHandler()
3733         htim->OC_DelayElapsedCallback(htim);  in HAL_TIM_IRQHandler()
3734         htim->PWM_PulseFinishedCallback(htim);  in HAL_TIM_IRQHandler()
3736         HAL_TIM_OC_DelayElapsedCallback(htim);  in HAL_TIM_IRQHandler()
3737         HAL_TIM_PWM_PulseFinishedCallback(htim);  in HAL_TIM_IRQHandler()
3740       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;  in HAL_TIM_IRQHandler()
3744   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)  in HAL_TIM_IRQHandler()
3746     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)  in HAL_TIM_IRQHandler()
3748       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);  in HAL_TIM_IRQHandler()
3749       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;  in HAL_TIM_IRQHandler()
3751       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)  in HAL_TIM_IRQHandler()
3754         htim->IC_CaptureCallback(htim);  in HAL_TIM_IRQHandler()
3756         HAL_TIM_IC_CaptureCallback(htim);  in HAL_TIM_IRQHandler()
3763         htim->OC_DelayElapsedCallback(htim);  in HAL_TIM_IRQHandler()
3764         htim->PWM_PulseFinishedCallback(htim);  in HAL_TIM_IRQHandler()
3766         HAL_TIM_OC_DelayElapsedCallback(htim);  in HAL_TIM_IRQHandler()
3767         HAL_TIM_PWM_PulseFinishedCallback(htim);  in HAL_TIM_IRQHandler()
3770       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;  in HAL_TIM_IRQHandler()
3774   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)  in HAL_TIM_IRQHandler()
3776     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)  in HAL_TIM_IRQHandler()
3778       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);  in HAL_TIM_IRQHandler()
3780       htim->PeriodElapsedCallback(htim);  in HAL_TIM_IRQHandler()
3782       HAL_TIM_PeriodElapsedCallback(htim);  in HAL_TIM_IRQHandler()
3787   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)  in HAL_TIM_IRQHandler()
3789     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)  in HAL_TIM_IRQHandler()
3791       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);  in HAL_TIM_IRQHandler()
3793       htim->TriggerCallback(htim);  in HAL_TIM_IRQHandler()
3795       HAL_TIM_TriggerCallback(htim);  in HAL_TIM_IRQHandler()
3836 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,  in HAL_TIM_OC_ConfigChannel()  argument
3848   __HAL_LOCK(htim);  in HAL_TIM_OC_ConfigChannel()
3855       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));  in HAL_TIM_OC_ConfigChannel()
3858       TIM_OC1_SetConfig(htim->Instance, sConfig);  in HAL_TIM_OC_ConfigChannel()
3865       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));  in HAL_TIM_OC_ConfigChannel()
3868       TIM_OC2_SetConfig(htim->Instance, sConfig);  in HAL_TIM_OC_ConfigChannel()
3875       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));  in HAL_TIM_OC_ConfigChannel()
3878       TIM_OC3_SetConfig(htim->Instance, sConfig);  in HAL_TIM_OC_ConfigChannel()
3885       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));  in HAL_TIM_OC_ConfigChannel()
3888       TIM_OC4_SetConfig(htim->Instance, sConfig);  in HAL_TIM_OC_ConfigChannel()
3897   __HAL_UNLOCK(htim);  in HAL_TIM_OC_ConfigChannel()
3915 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConf…  in HAL_TIM_IC_ConfigChannel()  argument
3920   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));  in HAL_TIM_IC_ConfigChannel()
3927   __HAL_LOCK(htim);  in HAL_TIM_IC_ConfigChannel()
3932     TIM_TI1_SetConfig(htim->Instance,  in HAL_TIM_IC_ConfigChannel()
3938     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;  in HAL_TIM_IC_ConfigChannel()
3941     htim->Instance->CCMR1 |= sConfig->ICPrescaler;  in HAL_TIM_IC_ConfigChannel()
3946     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));  in HAL_TIM_IC_ConfigChannel()
3948     TIM_TI2_SetConfig(htim->Instance,  in HAL_TIM_IC_ConfigChannel()
3954     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;  in HAL_TIM_IC_ConfigChannel()
3957     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);  in HAL_TIM_IC_ConfigChannel()
3962     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));  in HAL_TIM_IC_ConfigChannel()
3964     TIM_TI3_SetConfig(htim->Instance,  in HAL_TIM_IC_ConfigChannel()
3970     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;  in HAL_TIM_IC_ConfigChannel()
3973     htim->Instance->CCMR2 |= sConfig->ICPrescaler;  in HAL_TIM_IC_ConfigChannel()
3978     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));  in HAL_TIM_IC_ConfigChannel()
3980     TIM_TI4_SetConfig(htim->Instance,  in HAL_TIM_IC_ConfigChannel()
3986     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;  in HAL_TIM_IC_ConfigChannel()
3989     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);  in HAL_TIM_IC_ConfigChannel()
3996   __HAL_UNLOCK(htim);  in HAL_TIM_IC_ConfigChannel()
4014 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,  in HAL_TIM_PWM_ConfigChannel()  argument
4027   __HAL_LOCK(htim);  in HAL_TIM_PWM_ConfigChannel()
4034       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));  in HAL_TIM_PWM_ConfigChannel()
4037       TIM_OC1_SetConfig(htim->Instance, sConfig);  in HAL_TIM_PWM_ConfigChannel()
4040       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;  in HAL_TIM_PWM_ConfigChannel()
4043       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;  in HAL_TIM_PWM_ConfigChannel()
4044       htim->Instance->CCMR1 |= sConfig->OCFastMode;  in HAL_TIM_PWM_ConfigChannel()
4051       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));  in HAL_TIM_PWM_ConfigChannel()
4054       TIM_OC2_SetConfig(htim->Instance, sConfig);  in HAL_TIM_PWM_ConfigChannel()
4057       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;  in HAL_TIM_PWM_ConfigChannel()
4060       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;  in HAL_TIM_PWM_ConfigChannel()
4061       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;  in HAL_TIM_PWM_ConfigChannel()
4068       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));  in HAL_TIM_PWM_ConfigChannel()
4071       TIM_OC3_SetConfig(htim->Instance, sConfig);  in HAL_TIM_PWM_ConfigChannel()
4074       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;  in HAL_TIM_PWM_ConfigChannel()
4077       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;  in HAL_TIM_PWM_ConfigChannel()
4078       htim->Instance->CCMR2 |= sConfig->OCFastMode;  in HAL_TIM_PWM_ConfigChannel()
4085       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));  in HAL_TIM_PWM_ConfigChannel()
4088       TIM_OC4_SetConfig(htim->Instance, sConfig);  in HAL_TIM_PWM_ConfigChannel()
4091       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;  in HAL_TIM_PWM_ConfigChannel()
4094       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;  in HAL_TIM_PWM_ConfigChannel()
4095       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;  in HAL_TIM_PWM_ConfigChannel()
4104   __HAL_UNLOCK(htim);  in HAL_TIM_PWM_ConfigChannel()
4128 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef…  in HAL_TIM_OnePulse_ConfigChannel()  argument
4141     __HAL_LOCK(htim);  in HAL_TIM_OnePulse_ConfigChannel()
4143     htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_OnePulse_ConfigChannel()
4154         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));  in HAL_TIM_OnePulse_ConfigChannel()
4156         TIM_OC1_SetConfig(htim->Instance, &temp1);  in HAL_TIM_OnePulse_ConfigChannel()
4162         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));  in HAL_TIM_OnePulse_ConfigChannel()
4164         TIM_OC2_SetConfig(htim->Instance, &temp1);  in HAL_TIM_OnePulse_ConfigChannel()
4179           assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));  in HAL_TIM_OnePulse_ConfigChannel()
4181           TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,  in HAL_TIM_OnePulse_ConfigChannel()
4185           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;  in HAL_TIM_OnePulse_ConfigChannel()
4188           htim->Instance->SMCR &= ~TIM_SMCR_TS;  in HAL_TIM_OnePulse_ConfigChannel()
4189           htim->Instance->SMCR |= TIM_TS_TI1FP1;  in HAL_TIM_OnePulse_ConfigChannel()
4192           htim->Instance->SMCR &= ~TIM_SMCR_SMS;  in HAL_TIM_OnePulse_ConfigChannel()
4193           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;  in HAL_TIM_OnePulse_ConfigChannel()
4199           assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));  in HAL_TIM_OnePulse_ConfigChannel()
4201           TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,  in HAL_TIM_OnePulse_ConfigChannel()
4205           htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;  in HAL_TIM_OnePulse_ConfigChannel()
4208           htim->Instance->SMCR &= ~TIM_SMCR_TS;  in HAL_TIM_OnePulse_ConfigChannel()
4209           htim->Instance->SMCR |= TIM_TS_TI2FP2;  in HAL_TIM_OnePulse_ConfigChannel()
4212           htim->Instance->SMCR &= ~TIM_SMCR_SMS;  in HAL_TIM_OnePulse_ConfigChannel()
4213           htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;  in HAL_TIM_OnePulse_ConfigChannel()
4223     htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_OnePulse_ConfigChannel()
4225     __HAL_UNLOCK(htim);  in HAL_TIM_OnePulse_ConfigChannel()
4271 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,  in HAL_TIM_DMABurst_WriteStart()  argument
4276 …status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bu…  in HAL_TIM_DMABurst_WriteStart()
4321 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddre…  in HAL_TIM_DMABurst_MultiWriteStart()  argument
4328   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));  in HAL_TIM_DMABurst_MultiWriteStart()
4334   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)  in HAL_TIM_DMABurst_MultiWriteStart()
4338   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)  in HAL_TIM_DMABurst_MultiWriteStart()
4346       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;  in HAL_TIM_DMABurst_MultiWriteStart()
4359       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4360       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4363       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiWriteStart()
4366       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,  in HAL_TIM_DMABurst_MultiWriteStart()
4367                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)  in HAL_TIM_DMABurst_MultiWriteStart()
4377       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4378       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4381       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiWriteStart()
4384       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,  in HAL_TIM_DMABurst_MultiWriteStart()
4385                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)  in HAL_TIM_DMABurst_MultiWriteStart()
4395       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4396       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4399       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiWriteStart()
4402       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,  in HAL_TIM_DMABurst_MultiWriteStart()
4403                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)  in HAL_TIM_DMABurst_MultiWriteStart()
4413       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4414       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4417       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiWriteStart()
4420       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,  in HAL_TIM_DMABurst_MultiWriteStart()
4421                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)  in HAL_TIM_DMABurst_MultiWriteStart()
4431       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4432       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4435       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiWriteStart()
4438       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,  in HAL_TIM_DMABurst_MultiWriteStart()
4439                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)  in HAL_TIM_DMABurst_MultiWriteStart()
4449       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4450       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;  in HAL_TIM_DMABurst_MultiWriteStart()
4453       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiWriteStart()
4456       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,  in HAL_TIM_DMABurst_MultiWriteStart()
4457                            (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)  in HAL_TIM_DMABurst_MultiWriteStart()
4472     htim->Instance->DCR = (BurstBaseAddress | BurstLength);  in HAL_TIM_DMABurst_MultiWriteStart()
4474     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);  in HAL_TIM_DMABurst_MultiWriteStart()
4487 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)  in HAL_TIM_DMABurst_WriteStop()  argument
4499       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);  in HAL_TIM_DMABurst_WriteStop()
4504       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);  in HAL_TIM_DMABurst_WriteStop()
4509       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);  in HAL_TIM_DMABurst_WriteStop()
4514       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);  in HAL_TIM_DMABurst_WriteStop()
4519       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);  in HAL_TIM_DMABurst_WriteStop()
4524       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);  in HAL_TIM_DMABurst_WriteStop()
4535     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);  in HAL_TIM_DMABurst_WriteStop()
4538     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;  in HAL_TIM_DMABurst_WriteStop()
4581 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,  in HAL_TIM_DMABurst_ReadStart()  argument
4586 …status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bur…  in HAL_TIM_DMABurst_ReadStart()
4630 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddres…  in HAL_TIM_DMABurst_MultiReadStart()  argument
4637   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));  in HAL_TIM_DMABurst_MultiReadStart()
4643   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)  in HAL_TIM_DMABurst_MultiReadStart()
4647   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)  in HAL_TIM_DMABurst_MultiReadStart()
4655       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;  in HAL_TIM_DMABurst_MultiReadStart()
4667       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4668       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4671       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiReadStart()
4674 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)Bur…  in HAL_TIM_DMABurst_MultiReadStart()
4685       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4686       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4689       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiReadStart()
4692 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB…  in HAL_TIM_DMABurst_MultiReadStart()
4703       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4704       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4707       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiReadStart()
4710 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB…  in HAL_TIM_DMABurst_MultiReadStart()
4721       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4722       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4725       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiReadStart()
4728 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB…  in HAL_TIM_DMABurst_MultiReadStart()
4739       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4740       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4743       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiReadStart()
4746 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB…  in HAL_TIM_DMABurst_MultiReadStart()
4757       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4758       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;  in HAL_TIM_DMABurst_MultiReadStart()
4761       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;  in HAL_TIM_DMABurst_MultiReadStart()
4764 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)Bu…  in HAL_TIM_DMABurst_MultiReadStart()
4780     htim->Instance->DCR = (BurstBaseAddress | BurstLength);  in HAL_TIM_DMABurst_MultiReadStart()
4783     __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);  in HAL_TIM_DMABurst_MultiReadStart()
4796 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)  in HAL_TIM_DMABurst_ReadStop()  argument
4808       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);  in HAL_TIM_DMABurst_ReadStop()
4813       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);  in HAL_TIM_DMABurst_ReadStop()
4818       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);  in HAL_TIM_DMABurst_ReadStop()
4823       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);  in HAL_TIM_DMABurst_ReadStop()
4828       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);  in HAL_TIM_DMABurst_ReadStop()
4833       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);  in HAL_TIM_DMABurst_ReadStop()
4844     __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);  in HAL_TIM_DMABurst_ReadStop()
4847     htim->DMABurstState = HAL_DMA_BURST_STATE_READY;  in HAL_TIM_DMABurst_ReadStop()
4869 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)  in HAL_TIM_GenerateEvent()  argument
4872   assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_GenerateEvent()
4876   __HAL_LOCK(htim);  in HAL_TIM_GenerateEvent()
4879   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_GenerateEvent()
4882   htim->Instance->EGR = EventSource;  in HAL_TIM_GenerateEvent()
4885   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_GenerateEvent()
4887   __HAL_UNLOCK(htim);  in HAL_TIM_GenerateEvent()
4906 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,  in HAL_TIM_ConfigOCrefClear()  argument
4913   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));  in HAL_TIM_ConfigOCrefClear()
4917   __HAL_LOCK(htim);  in HAL_TIM_ConfigOCrefClear()
4919   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_ConfigOCrefClear()
4926       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));  in HAL_TIM_ConfigOCrefClear()
4940         htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_ConfigOCrefClear()
4941         __HAL_UNLOCK(htim);  in HAL_TIM_ConfigOCrefClear()
4945       TIM_ETR_SetConfig(htim->Instance,  in HAL_TIM_ConfigOCrefClear()
4966           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);  in HAL_TIM_ConfigOCrefClear()
4971           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);  in HAL_TIM_ConfigOCrefClear()
4980           SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);  in HAL_TIM_ConfigOCrefClear()
4985           CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);  in HAL_TIM_ConfigOCrefClear()
4994           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);  in HAL_TIM_ConfigOCrefClear()
4999           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);  in HAL_TIM_ConfigOCrefClear()
5008           SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);  in HAL_TIM_ConfigOCrefClear()
5013           CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);  in HAL_TIM_ConfigOCrefClear()
5022   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_ConfigOCrefClear()
5024   __HAL_UNLOCK(htim);  in HAL_TIM_ConfigOCrefClear()
5036 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *…  in HAL_TIM_ConfigClockSource()  argument
5042   __HAL_LOCK(htim);  in HAL_TIM_ConfigClockSource()
5044   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_ConfigClockSource()
5050   tmpsmcr = htim->Instance->SMCR;  in HAL_TIM_ConfigClockSource()
5053   htim->Instance->SMCR = tmpsmcr;  in HAL_TIM_ConfigClockSource()
5059       assert_param(IS_TIM_INSTANCE(htim->Instance));  in HAL_TIM_ConfigClockSource()
5066       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));  in HAL_TIM_ConfigClockSource()
5074       TIM_ETR_SetConfig(htim->Instance,  in HAL_TIM_ConfigClockSource()
5080       tmpsmcr = htim->Instance->SMCR;  in HAL_TIM_ConfigClockSource()
5083       htim->Instance->SMCR = tmpsmcr;  in HAL_TIM_ConfigClockSource()
5090       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));  in HAL_TIM_ConfigClockSource()
5098       TIM_ETR_SetConfig(htim->Instance,  in HAL_TIM_ConfigClockSource()
5103       htim->Instance->SMCR |= TIM_SMCR_ECE;  in HAL_TIM_ConfigClockSource()
5110       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));  in HAL_TIM_ConfigClockSource()
5116       TIM_TI1_ConfigInputStage(htim->Instance,  in HAL_TIM_ConfigClockSource()
5119       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);  in HAL_TIM_ConfigClockSource()
5126       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));  in HAL_TIM_ConfigClockSource()
5132       TIM_TI2_ConfigInputStage(htim->Instance,  in HAL_TIM_ConfigClockSource()
5135       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);  in HAL_TIM_ConfigClockSource()
5142       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));  in HAL_TIM_ConfigClockSource()
5148       TIM_TI1_ConfigInputStage(htim->Instance,  in HAL_TIM_ConfigClockSource()
5151       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);  in HAL_TIM_ConfigClockSource()
5161       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));  in HAL_TIM_ConfigClockSource()
5163       TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);  in HAL_TIM_ConfigClockSource()
5171   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_ConfigClockSource()
5173   __HAL_UNLOCK(htim);  in HAL_TIM_ConfigClockSource()
5190 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)  in HAL_TIM_ConfigTI1Input()  argument
5195   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));  in HAL_TIM_ConfigTI1Input()
5199   tmpcr2 = htim->Instance->CR2;  in HAL_TIM_ConfigTI1Input()
5208   htim->Instance->CR2 = tmpcr2;  in HAL_TIM_ConfigTI1Input()
5222 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef …  in HAL_TIM_SlaveConfigSynchro()  argument
5225   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));  in HAL_TIM_SlaveConfigSynchro()
5229   __HAL_LOCK(htim);  in HAL_TIM_SlaveConfigSynchro()
5231   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_SlaveConfigSynchro()
5233   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)  in HAL_TIM_SlaveConfigSynchro()
5235     htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_SlaveConfigSynchro()
5236     __HAL_UNLOCK(htim);  in HAL_TIM_SlaveConfigSynchro()
5241   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);  in HAL_TIM_SlaveConfigSynchro()
5244   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);  in HAL_TIM_SlaveConfigSynchro()
5246   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_SlaveConfigSynchro()
5248   __HAL_UNLOCK(htim);  in HAL_TIM_SlaveConfigSynchro()
5262 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,  in HAL_TIM_SlaveConfigSynchro_IT()  argument
5266   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));  in HAL_TIM_SlaveConfigSynchro_IT()
5270   __HAL_LOCK(htim);  in HAL_TIM_SlaveConfigSynchro_IT()
5272   htim->State = HAL_TIM_STATE_BUSY;  in HAL_TIM_SlaveConfigSynchro_IT()
5274   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)  in HAL_TIM_SlaveConfigSynchro_IT()
5276     htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_SlaveConfigSynchro_IT()
5277     __HAL_UNLOCK(htim);  in HAL_TIM_SlaveConfigSynchro_IT()
5282   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);  in HAL_TIM_SlaveConfigSynchro_IT()
5285   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);  in HAL_TIM_SlaveConfigSynchro_IT()
5287   htim->State = HAL_TIM_STATE_READY;  in HAL_TIM_SlaveConfigSynchro_IT()
5289   __HAL_UNLOCK(htim);  in HAL_TIM_SlaveConfigSynchro_IT()
5305 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)  in HAL_TIM_ReadCapturedValue()  argument
5314       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));  in HAL_TIM_ReadCapturedValue()
5317       tmpreg =  htim->Instance->CCR1;  in HAL_TIM_ReadCapturedValue()
5324       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));  in HAL_TIM_ReadCapturedValue()
5327       tmpreg =   htim->Instance->CCR2;  in HAL_TIM_ReadCapturedValue()
5335       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));  in HAL_TIM_ReadCapturedValue()
5338       tmpreg =   htim->Instance->CCR3;  in HAL_TIM_ReadCapturedValue()
5346       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));  in HAL_TIM_ReadCapturedValue()
5349       tmpreg =   htim->Instance->CCR4;  in HAL_TIM_ReadCapturedValue()
5389 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)  in HAL_TIM_PeriodElapsedCallback()  argument
5392   UNUSED(htim);  in HAL_TIM_PeriodElapsedCallback()
5404 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)  in HAL_TIM_PeriodElapsedHalfCpltCallback()  argument
5407   UNUSED(htim);  in HAL_TIM_PeriodElapsedHalfCpltCallback()
5419 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)  in HAL_TIM_OC_DelayElapsedCallback()  argument
5422   UNUSED(htim);  in HAL_TIM_OC_DelayElapsedCallback()
5434 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)  in HAL_TIM_IC_CaptureCallback()  argument
5437   UNUSED(htim);  in HAL_TIM_IC_CaptureCallback()
5449 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)  in HAL_TIM_IC_CaptureHalfCpltCallback()  argument
5452   UNUSED(htim);  in HAL_TIM_IC_CaptureHalfCpltCallback()
5464 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)  in HAL_TIM_PWM_PulseFinishedCallback()  argument
5467   UNUSED(htim);  in HAL_TIM_PWM_PulseFinishedCallback()
5479 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)  in HAL_TIM_PWM_PulseFinishedHalfCpltCallback()  argument
5482   UNUSED(htim);  in HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
5494 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)  in HAL_TIM_TriggerCallback()  argument
5497   UNUSED(htim);  in HAL_TIM_TriggerCallback()
5509 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)  in HAL_TIM_TriggerHalfCpltCallback()  argument
5512   UNUSED(htim);  in HAL_TIM_TriggerHalfCpltCallback()
5524 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)  in HAL_TIM_ErrorCallback()  argument
5527   UNUSED(htim);  in HAL_TIM_ErrorCallback()
5565 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Callb…  in HAL_TIM_RegisterCallback()  argument
5575   if (htim->State == HAL_TIM_STATE_READY)  in HAL_TIM_RegisterCallback()
5580         htim->Base_MspInitCallback                 = pCallback;  in HAL_TIM_RegisterCallback()
5584         htim->Base_MspDeInitCallback               = pCallback;  in HAL_TIM_RegisterCallback()
5588         htim->IC_MspInitCallback                   = pCallback;  in HAL_TIM_RegisterCallback()
5592         htim->IC_MspDeInitCallback                 = pCallback;  in HAL_TIM_RegisterCallback()
5596         htim->OC_MspInitCallback                   = pCallback;  in HAL_TIM_RegisterCallback()
5600         htim->OC_MspDeInitCallback                 = pCallback;  in HAL_TIM_RegisterCallback()
5604         htim->PWM_MspInitCallback                  = pCallback;  in HAL_TIM_RegisterCallback()
5608         htim->PWM_MspDeInitCallback                = pCallback;  in HAL_TIM_RegisterCallback()
5612         htim->OnePulse_MspInitCallback             = pCallback;  in HAL_TIM_RegisterCallback()
5616         htim->OnePulse_MspDeInitCallback           = pCallback;  in HAL_TIM_RegisterCallback()
5620         htim->Encoder_MspInitCallback              = pCallback;  in HAL_TIM_RegisterCallback()
5624         htim->Encoder_MspDeInitCallback            = pCallback;  in HAL_TIM_RegisterCallback()
5628         htim->PeriodElapsedCallback                = pCallback;  in HAL_TIM_RegisterCallback()
5632         htim->PeriodElapsedHalfCpltCallback        = pCallback;  in HAL_TIM_RegisterCallback()
5636         htim->TriggerCallback                      = pCallback;  in HAL_TIM_RegisterCallback()
5640         htim->TriggerHalfCpltCallback              = pCallback;  in HAL_TIM_RegisterCallback()
5644         htim->IC_CaptureCallback                   = pCallback;  in HAL_TIM_RegisterCallback()
5648         htim->IC_CaptureHalfCpltCallback           = pCallback;  in HAL_TIM_RegisterCallback()
5652         htim->OC_DelayElapsedCallback              = pCallback;  in HAL_TIM_RegisterCallback()
5656         htim->PWM_PulseFinishedCallback            = pCallback;  in HAL_TIM_RegisterCallback()
5660         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;  in HAL_TIM_RegisterCallback()
5664         htim->ErrorCallback                        = pCallback;  in HAL_TIM_RegisterCallback()
5673   else if (htim->State == HAL_TIM_STATE_RESET)  in HAL_TIM_RegisterCallback()
5678         htim->Base_MspInitCallback         = pCallback;  in HAL_TIM_RegisterCallback()
5682         htim->Base_MspDeInitCallback       = pCallback;  in HAL_TIM_RegisterCallback()
5686         htim->IC_MspInitCallback           = pCallback;  in HAL_TIM_RegisterCallback()
5690         htim->IC_MspDeInitCallback         = pCallback;  in HAL_TIM_RegisterCallback()
5694         htim->OC_MspInitCallback           = pCallback;  in HAL_TIM_RegisterCallback()
5698         htim->OC_MspDeInitCallback         = pCallback;  in HAL_TIM_RegisterCallback()
5702         htim->PWM_MspInitCallback          = pCallback;  in HAL_TIM_RegisterCallback()
5706         htim->PWM_MspDeInitCallback        = pCallback;  in HAL_TIM_RegisterCallback()
5710         htim->OnePulse_MspInitCallback     = pCallback;  in HAL_TIM_RegisterCallback()
5714         htim->OnePulse_MspDeInitCallback   = pCallback;  in HAL_TIM_RegisterCallback()
5718         htim->Encoder_MspInitCallback      = pCallback;  in HAL_TIM_RegisterCallback()
5722         htim->Encoder_MspDeInitCallback    = pCallback;  in HAL_TIM_RegisterCallback()
5770 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Cal…  in HAL_TIM_UnRegisterCallback()  argument
5774   if (htim->State == HAL_TIM_STATE_READY)  in HAL_TIM_UnRegisterCallback()
5780         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;  in HAL_TIM_UnRegisterCallback()
5785         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5790         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;  in HAL_TIM_UnRegisterCallback()
5795         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5800         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;  in HAL_TIM_UnRegisterCallback()
5805         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5810         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;  in HAL_TIM_UnRegisterCallback()
5815         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5820         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;  in HAL_TIM_UnRegisterCallback()
5825         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5830         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;  in HAL_TIM_UnRegisterCallback()
5835         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5840         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;  in HAL_TIM_UnRegisterCallback()
5845         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;  in HAL_TIM_UnRegisterCallback()
5850         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;  in HAL_TIM_UnRegisterCallback()
5855         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;  in HAL_TIM_UnRegisterCallback()
5860         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;  in HAL_TIM_UnRegisterCallback()
5865         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;  in HAL_TIM_UnRegisterCallback()
5870         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;  in HAL_TIM_UnRegisterCallback()
5875         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;  in HAL_TIM_UnRegisterCallback()
5880         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;  in HAL_TIM_UnRegisterCallback()
5885         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;  in HAL_TIM_UnRegisterCallback()
5894   else if (htim->State == HAL_TIM_STATE_RESET)  in HAL_TIM_UnRegisterCallback()
5900         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;  in HAL_TIM_UnRegisterCallback()
5905         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5910         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;  in HAL_TIM_UnRegisterCallback()
5915         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5920         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;  in HAL_TIM_UnRegisterCallback()
5925         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5930         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;  in HAL_TIM_UnRegisterCallback()
5935         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5940         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;  in HAL_TIM_UnRegisterCallback()
5945         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5950         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;  in HAL_TIM_UnRegisterCallback()
5955         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;  in HAL_TIM_UnRegisterCallback()
5998 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)  in HAL_TIM_Base_GetState()  argument
6000   return htim->State;  in HAL_TIM_Base_GetState()
6008 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)  in HAL_TIM_OC_GetState()  argument
6010   return htim->State;  in HAL_TIM_OC_GetState()
6018 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)  in HAL_TIM_PWM_GetState()  argument
6020   return htim->State;  in HAL_TIM_PWM_GetState()
6028 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)  in HAL_TIM_IC_GetState()  argument
6030   return htim->State;  in HAL_TIM_IC_GetState()
6038 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)  in HAL_TIM_OnePulse_GetState()  argument
6040   return htim->State;  in HAL_TIM_OnePulse_GetState()
6048 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)  in HAL_TIM_Encoder_GetState()  argument
6050   return htim->State;  in HAL_TIM_Encoder_GetState()
6058 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)  in HAL_TIM_GetActiveChannel()  argument
6060   return htim->Channel;  in HAL_TIM_GetActiveChannel()
6076 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channe…  in HAL_TIM_GetChannelState()  argument
6081   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));  in HAL_TIM_GetChannelState()
6083   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);  in HAL_TIM_GetChannelState()
6093 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)  in HAL_TIM_DMABurstState()  argument
6096   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));  in HAL_TIM_DMABurstState()
6098   return htim->DMABurstState;  in HAL_TIM_DMABurstState()
6120   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;  in TIM_DMAError()  local
6122   if (hdma == htim->hdma[TIM_DMA_ID_CC1])  in TIM_DMAError()
6124     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;  in TIM_DMAError()
6125     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMAError()
6127   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])  in TIM_DMAError()
6129     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;  in TIM_DMAError()
6130     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMAError()
6132   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])  in TIM_DMAError()
6134     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;  in TIM_DMAError()
6135     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMAError()
6137   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])  in TIM_DMAError()
6139     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;  in TIM_DMAError()
6140     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMAError()
6144     htim->State = HAL_TIM_STATE_READY;  in TIM_DMAError()
6148   htim->ErrorCallback(htim);  in TIM_DMAError()
6150   HAL_TIM_ErrorCallback(htim);  in TIM_DMAError()
6153   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;  in TIM_DMAError()
6163   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;  in TIM_DMADelayPulseCplt()  local
6165   if (hdma == htim->hdma[TIM_DMA_ID_CC1])  in TIM_DMADelayPulseCplt()
6167     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;  in TIM_DMADelayPulseCplt()
6171       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMADelayPulseCplt()
6174   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])  in TIM_DMADelayPulseCplt()
6176     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;  in TIM_DMADelayPulseCplt()
6180       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMADelayPulseCplt()
6183   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])  in TIM_DMADelayPulseCplt()
6185     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;  in TIM_DMADelayPulseCplt()
6189       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMADelayPulseCplt()
6192   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])  in TIM_DMADelayPulseCplt()
6194     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;  in TIM_DMADelayPulseCplt()
6198       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMADelayPulseCplt()
6207   htim->PWM_PulseFinishedCallback(htim);  in TIM_DMADelayPulseCplt()
6209   HAL_TIM_PWM_PulseFinishedCallback(htim);  in TIM_DMADelayPulseCplt()
6212   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;  in TIM_DMADelayPulseCplt()
6222   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;  in TIM_DMADelayPulseHalfCplt()  local
6224   if (hdma == htim->hdma[TIM_DMA_ID_CC1])  in TIM_DMADelayPulseHalfCplt()
6226     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;  in TIM_DMADelayPulseHalfCplt()
6228   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])  in TIM_DMADelayPulseHalfCplt()
6230     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;  in TIM_DMADelayPulseHalfCplt()
6232   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])  in TIM_DMADelayPulseHalfCplt()
6234     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;  in TIM_DMADelayPulseHalfCplt()
6236   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])  in TIM_DMADelayPulseHalfCplt()
6238     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;  in TIM_DMADelayPulseHalfCplt()
6246   htim->PWM_PulseFinishedHalfCpltCallback(htim);  in TIM_DMADelayPulseHalfCplt()
6248   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);  in TIM_DMADelayPulseHalfCplt()
6251   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;  in TIM_DMADelayPulseHalfCplt()
6261   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;  in TIM_DMACaptureCplt()  local
6263   if (hdma == htim->hdma[TIM_DMA_ID_CC1])  in TIM_DMACaptureCplt()
6265     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;  in TIM_DMACaptureCplt()
6269       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMACaptureCplt()
6272   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])  in TIM_DMACaptureCplt()
6274     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;  in TIM_DMACaptureCplt()
6278       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMACaptureCplt()
6281   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])  in TIM_DMACaptureCplt()
6283     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;  in TIM_DMACaptureCplt()
6287       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMACaptureCplt()
6290   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])  in TIM_DMACaptureCplt()
6292     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;  in TIM_DMACaptureCplt()
6296       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);  in TIM_DMACaptureCplt()
6305   htim->IC_CaptureCallback(htim);  in TIM_DMACaptureCplt()
6307   HAL_TIM_IC_CaptureCallback(htim);  in TIM_DMACaptureCplt()
6310   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;  in TIM_DMACaptureCplt()
6320   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;  in TIM_DMACaptureHalfCplt()  local
6322   if (hdma == htim->hdma[TIM_DMA_ID_CC1])  in TIM_DMACaptureHalfCplt()
6324     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;  in TIM_DMACaptureHalfCplt()
6326   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])  in TIM_DMACaptureHalfCplt()
6328     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;  in TIM_DMACaptureHalfCplt()
6330   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])  in TIM_DMACaptureHalfCplt()
6332     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;  in TIM_DMACaptureHalfCplt()
6334   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])  in TIM_DMACaptureHalfCplt()
6336     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;  in TIM_DMACaptureHalfCplt()
6344   htim->IC_CaptureHalfCpltCallback(htim);  in TIM_DMACaptureHalfCplt()
6346   HAL_TIM_IC_CaptureHalfCpltCallback(htim);  in TIM_DMACaptureHalfCplt()
6349   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;  in TIM_DMACaptureHalfCplt()
6359   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;  in TIM_DMAPeriodElapsedCplt()  local
6361   if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)  in TIM_DMAPeriodElapsedCplt()
6363     htim->State = HAL_TIM_STATE_READY;  in TIM_DMAPeriodElapsedCplt()
6367   htim->PeriodElapsedCallback(htim);  in TIM_DMAPeriodElapsedCplt()
6369   HAL_TIM_PeriodElapsedCallback(htim);  in TIM_DMAPeriodElapsedCplt()
6380   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;  in TIM_DMAPeriodElapsedHalfCplt()  local
6383   htim->PeriodElapsedHalfCpltCallback(htim);  in TIM_DMAPeriodElapsedHalfCplt()
6385   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);  in TIM_DMAPeriodElapsedHalfCplt()
6396   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;  in TIM_DMATriggerCplt()  local
6398   if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)  in TIM_DMATriggerCplt()
6400     htim->State = HAL_TIM_STATE_READY;  in TIM_DMATriggerCplt()
6404   htim->TriggerCallback(htim);  in TIM_DMATriggerCplt()
6406   HAL_TIM_TriggerCallback(htim);  in TIM_DMATriggerCplt()
6417   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;  in TIM_DMATriggerHalfCplt()  local
6420   htim->TriggerHalfCpltCallback(htim);  in TIM_DMATriggerHalfCplt()
6422   HAL_TIM_TriggerHalfCpltCallback(htim);  in TIM_DMATriggerHalfCplt()
6664 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,  in TIM_SlaveTimer_SetConfig()  argument
6673   tmpsmcr = htim->Instance->SMCR;  in TIM_SlaveTimer_SetConfig()
6686   htim->Instance->SMCR = tmpsmcr;  in TIM_SlaveTimer_SetConfig()
6694       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));  in TIM_SlaveTimer_SetConfig()
6699       TIM_ETR_SetConfig(htim->Instance,  in TIM_SlaveTimer_SetConfig()
6709       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));  in TIM_SlaveTimer_SetConfig()
6718       tmpccer = htim->Instance->CCER;  in TIM_SlaveTimer_SetConfig()
6719       htim->Instance->CCER &= ~TIM_CCER_CC1E;  in TIM_SlaveTimer_SetConfig()
6720       tmpccmr1 = htim->Instance->CCMR1;  in TIM_SlaveTimer_SetConfig()
6727       htim->Instance->CCMR1 = tmpccmr1;  in TIM_SlaveTimer_SetConfig()
6728       htim->Instance->CCER = tmpccer;  in TIM_SlaveTimer_SetConfig()
6735       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));  in TIM_SlaveTimer_SetConfig()
6740       TIM_TI1_ConfigInputStage(htim->Instance,  in TIM_SlaveTimer_SetConfig()
6749       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));  in TIM_SlaveTimer_SetConfig()
6754       TIM_TI2_ConfigInputStage(htim->Instance,  in TIM_SlaveTimer_SetConfig()
6766       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));  in TIM_SlaveTimer_SetConfig()
7146 void TIM_ResetCallback(TIM_HandleTypeDef *htim)  in TIM_ResetCallback()  argument
7149   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;  in TIM_ResetCallback()
7150   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;  in TIM_ResetCallback()
7151   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;  in TIM_ResetCallback()
7152   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;  in TIM_ResetCallback()
7153   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;  in TIM_ResetCallback()
7154   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;  in TIM_ResetCallback()
7155   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;  in TIM_ResetCallback()
7156   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;  in TIM_ResetCallback()
7157   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;  in TIM_ResetCallback()
7158   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;  in TIM_ResetCallback()