2801   SET_BIT(TIMx->DIER, TIM_DIER_UIE);  in LL_TIM_EnableIT_UPDATE()
2812   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);  in LL_TIM_DisableIT_UPDATE()
2823   return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledIT_UPDATE()
2834   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);  in LL_TIM_EnableIT_CC1()
2845   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);  in LL_TIM_DisableIT_CC1()
2856   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledIT_CC1()
2867   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);  in LL_TIM_EnableIT_CC2()
2878   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);  in LL_TIM_DisableIT_CC2()
2889   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledIT_CC2()
2900   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);  in LL_TIM_EnableIT_CC3()
2911   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);  in LL_TIM_DisableIT_CC3()
2922   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledIT_CC3()
2933   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);  in LL_TIM_EnableIT_CC4()
2944   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);  in LL_TIM_DisableIT_CC4()
2955   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledIT_CC4()
2966   SET_BIT(TIMx->DIER, TIM_DIER_TIE);  in LL_TIM_EnableIT_TRIG()
2977   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);  in LL_TIM_DisableIT_TRIG()
2988   return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledIT_TRIG()
3006   SET_BIT(TIMx->DIER, TIM_DIER_UDE);  in LL_TIM_EnableDMAReq_UPDATE()
3017   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);  in LL_TIM_DisableDMAReq_UPDATE()
3028   return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledDMAReq_UPDATE()
3039   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);  in LL_TIM_EnableDMAReq_CC1()
3050   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);  in LL_TIM_DisableDMAReq_CC1()
3061   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledDMAReq_CC1()
3072   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);  in LL_TIM_EnableDMAReq_CC2()
3083   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);  in LL_TIM_DisableDMAReq_CC2()
3094   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledDMAReq_CC2()
3105   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);  in LL_TIM_EnableDMAReq_CC3()
3116   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);  in LL_TIM_DisableDMAReq_CC3()
3127   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledDMAReq_CC3()
3138   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);  in LL_TIM_EnableDMAReq_CC4()
3149   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);  in LL_TIM_DisableDMAReq_CC4()
3160   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledDMAReq_CC4()
3171   SET_BIT(TIMx->DIER, TIM_DIER_TDE);  in LL_TIM_EnableDMAReq_TRIG()
3182   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);  in LL_TIM_DisableDMAReq_TRIG()
3193   return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);  in LL_TIM_IsEnabledDMAReq_TRIG()