Lines Matching +full:fail +full:- +full:fast
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
50 /****** Cortex-M Processor Exceptions Numbers ****************************************************…
51 …NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt …
52 …HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt …
53 …MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt …
54 …BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt …
55 …UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt …
56 …SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt …
57 …DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt …
58 …PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt …
59 …SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt …
152 …CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt …
155 …SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt …
205 …WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins …
222 * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
225 #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
231 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
234 #define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
241 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
274 …__IO uint32_t PCSEL; /*!< ADC pre-channel selection, A…
287 …uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C …
292 …uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C …
297 …uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C …
318 __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1…
328 __IO uint32_t CTR; /*!< ART accelerator - control register */
360 …[4]; /*!< Reserved, 0x030 - 0x03C */
369 …[8]; /*!< Reserved, 0x060 - 0x07C */
396 …[2]; /*!< Reserved, 0x0E8 - 0x0EC */
426 …__IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x…
494 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
495 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
496 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
497 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
498 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
499 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
500 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
501 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
502 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
699 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
700 …t32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
701 …t32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
935 * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
936 * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
986 …__IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Addr…
1005 …__IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Addr…
1014 … BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
1023 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1061 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
1062 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
1077 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
1082 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
1104 …CR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
1111 …uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 …
1113 …uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC …
1136 * @brief Inter-integrated Circuit Interface
1181 …ved20[4]; /* Reserved Address offset: 20h-2Ch */
1188 …ved48[2]; /* Reserved Address offset: 48h-4Ch */
1189 …MEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1190 …MEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1191 …MEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1192 …MEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1193 …UFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1194 …UFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1195 …UFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1196 …HTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1198 …UFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
1199 …UFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
1200 …UFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1201 …UFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1206 * @brief LCD-TFT Display Controller
1211 …uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 …
1217 …uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 …
1231 * @brief LCD-TFT Display layer x Controller
1321 …uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC …
1342 …uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C …
1368 …uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C A…
1373 * @brief Real-Time Clock
1391 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address …
1438 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1456 * @brief SPDIF-RX Interface
1495 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
1500 …uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C …
1502 …uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 …
1523 …__IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-…
1524 …__IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-…
1533 …2_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
1562 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
1564 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
1610 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1616 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1757 …__IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address o…
1758 …__IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address o…
1759 …__IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address o…
1760 …__IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address o…
1788 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1791 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1792 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
1801 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
2021 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
2050 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
2056 * @brief USB_OTG_IN_Endpoint-Specific_Register
2067 …uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
2072 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2082 …uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1…
2124 … Address offset: 0x00-0x1FCC */
2125 …__IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, …
2129 …__IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, …
2130 …__IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, …
2131 …__IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, …
2132 …__IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, …
2133 …__IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, …
2134 …__IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, …
2135 …__IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, …
2136 …__IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, …
2137 … Address offset: 0x2000-0x2004 */
2138 …__IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing function…
2139 … Address offset: 0x200C-0x2020 */
2140 …__IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 regis…
2142 …__IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modific…
2143 … Address offset: 0x2030-0x2104 */
2144 …__IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modificati…
2145 … Address offset: 0x210C-0x3004 */
2146 …__IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing function…
2147 … Address offset: 0x300C-0x3020 */
2148 …__IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 regis…
2150 …__IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modific…
2151 … Address offset: 0x3030-0x3104 */
2152 …__IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modificati…
2153 … Address offset: 0x310C-0x4004 */
2154 …__IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functio…
2155 … Address offset: 0x400C-0x5004 */
2156 …__IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing function…
2157 … Address offset: 0x500C-0x6004 */
2158 …__IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing function…
2159 … Address offset: 0x600C-0x7004 */
2160 …__IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing function…
2161 … Address offset: 0x700C-0x8004 */
2162 …__IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing function…
2163 … Address offset: 0x800C-0x8020 */
2164 …__IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 regis…
2166 …__IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modific…
2167 … Address offset: 0x8030-0x8104 */
2168 …__IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modificati…
2169 … Address offset: 0x810C-0x42020 */
2170 …__IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 regi…
2171 …__IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification re…
2172 … Address offset: 0x4202C-0x420FC */
2173 …__IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, …
2174 …__IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, …
2175 …__IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modificatio…
2176 … Address offset: 0x4210C-0x430FC */
2177 …__IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, …
2178 …__IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, …
2179 …__IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modificatio…
2180 … Address offset: 0x4310C-0x44020 */
2181 …__IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 regi…
2182 …__IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification re…
2183 … Address offset: 0x4402C-0x440FC */
2184 …__IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, …
2185 …__IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, …
2186 …__IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modificatio…
2187 … Address offset: 0x4410C-0x450FC */
2188 …__IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, …
2189 …__IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, …
2190 …__IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modificatio…
2191 … Address offset: 0x4510C-0x460FC */
2192 …__IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, …
2193 …__IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, …
2194 …__IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modificatio…
2195 … Address offset: 0x4610C-0x470FC */
2196 …__IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, …
2197 …__IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, …
2198 …__IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modificatio…
2199 … Address offset: 0x4710C-0x480FC */
2200 …__IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, …
2201 …__IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, …
2202 …__IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modificatio…
2217 …UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
2219 #define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI-…
2220 … (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge …
3146 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift…
3149 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift…
3152 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift…
3155 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift…
3981 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
4242 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
4722 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-match…
4725 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-match…
5564 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
5629 /* HDMI-CEC (CEC) */
5686 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Rec…
5692 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun …
5716 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer U…
5719 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error …
5727 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Rec…
5733 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun …
5757 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer U…
5760 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT…
5778 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data registe…
6121 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-…
6126 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-…
6131 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-b…
6136 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-…
6141 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-…
6146 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-b…
6151 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-…
6154 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-…
6159 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-…
6162 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-…
6167 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-b…
6170 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-b…
6501 …FFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offse…
6504 … DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6540 …_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6543 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion…
6750 …_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting co…
7058 #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap …
7090 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet spe…
7099 … ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
7111 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit ma…
7135 #define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Pa…
7138 #define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Pa…
7158 #define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP …
7180 …wards all control frames except Pause packets to application even if they fail the Address Filter …
7183 …ARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter …
7286 #define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-…
7289 #define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
7295 #define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLA…
7320 #define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN …
7356 #define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN …
7392 #define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quan…
7502 #define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up …
7505 #define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FI…
7508 #define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Pa…
7514 #define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Pa…
7520 #define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Pa…
7528 /* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7531 #define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet fi…
7589 #define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Vers…
7592 #define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined …
7646 …R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7649 …0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7652 …R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7664 #define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Ti…
7676 #define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-u…
7688 #define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Suppo…
7732 #define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestam…
7955 #define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset…
8177 … ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
8180 … ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
8209 /* Bit definition for Ethernet MAC Sub-second Increment Register */
8212 #define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Incre…
8215 #define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond …
8225 #define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-second…
8238 #define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-secon…
8314 #define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timesta…
8319 #define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timesta…
8507 …MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
8510 … ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
8554 …QDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
8558 … ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deact…
8561 … ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activ…
8627 #define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned B…
9637 #define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sam…
10976 #define DUAL_BANK /* Dual-bank Flash */
11041 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program …
11091 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program …
11221 #define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk /*!< Arm Cortex-M4 b…
11224 #define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk /*!< Arm Cortex-M7 b…
11233 …SLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status …
11260 …AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start statu…
11263 #define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-o…
11276 …M7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */
11279 …M7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */
11284 …M4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk /*!< Arm Cortex-M4 boot address 0 */
11287 …M4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk /*!< Arm Cortex-M4 boot address 1 */
11426 … FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
11434 … FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11485 … FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
11493 … FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11804 … FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
13575 /* Inter-integrated Circuit Interface (I2C) */
13649 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
13652 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
13681 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
13843 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
13848 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
14143 /* LCD-TFT Display Controller (LTDC) */
14187 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT control…
14618 … MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
14930 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up…
15059 … /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
15094 … /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
17339 /* Real-Time Clock (RTC) */
18098 /* SPDIF-RX Interface */
18134 … SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchron…
18198 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error …
18915 …KFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) …
18997 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail…
19000 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail In…
19054 …AILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
19174 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode …
19180 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polyn…
19268 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Dat…
19359 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet availa…
19362 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space …
19377 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet availa…
19760 #define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode …
19763 #define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode …
19766 #define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode …
19769 #define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode …
19772 #define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mo…
19775 #define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mo…
19778 #define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mo…
19781 #define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mo…
20099 #define SYSCFG_CFGR_CM4L SYSCFG_CFGR_CM4L_Msk /*!<Cortex-M4 LOCKUP…
20108 #define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk /*!<Cortex-M7 LOCKUP…
20146 …G_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk /*!< High-speed at low-voltage */
20184 #define SYSCFG_UR1_BCM4 SYSCFG_UR1_BCM4_Msk /*!< Boot Cortex-M4 …
20187 #define SYSCFG_UR1_BCM7 SYSCFG_UR1_BCM7_Msk /*!< Boot Cortex-M7 …
20196 #define SYSCFG_UR2_BCM7_ADD0 SYSCFG_UR2_BCM7_ADD0_Msk /*!< Boot Cortex-M7 …
20200 #define SYSCFG_UR3_BCM7_ADD1 SYSCFG_UR3_BCM7_ADD1_Msk /*!< Boot Cortex-M7 …
20204 #define SYSCFG_UR3_BCM4_ADD0 SYSCFG_UR3_BCM4_ADD0_Msk /*!< Boot Cortex-M4 …
20210 #define SYSCFG_UR4_BCM4_ADD1 SYSCFG_UR4_BCM4_ADD1_Msk /*!< Boot Cortex-M4 …
20345 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
20351 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload prel…
20599 …R1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
20624 …R1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
20641 /*----------------------------------------------------------------------------*/
20680 …R2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
20705 …R2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
20722 /*----------------------------------------------------------------------------*/
20825 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-relo…
20874 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
20892 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
20895 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
20950 …R3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
20969 …R3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
21559 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - B…
21568 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
21593 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - B…
21617 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit …
21661 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate …
21664 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
21669 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-O…
21683 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power …
21686 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Sel…
21725 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
21786 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate …
21845 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate …
21848 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate …
22118 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
22134 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
22629 #define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull…
22736 …MISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
22739 …_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
24463 #define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
24491 …EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
24508 …EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
24525 …EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
24542 …EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
24559 …EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
25332 …DATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
25411 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral se…
25414 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral se…
25417 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral se…
25420 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral se…
25444 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid…
25447 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid…
25464 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only…
25475 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length …
25534 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeou…
25573 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on progra…
25644 … USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed …
25647 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
25650 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
25661 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power c…
25667 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resum…
25812 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SE…
26201 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up dete…
26479 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed devic…
26772 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SE…
27206 /******************** TIM Instances : Advanced-control timers *****************/
27210 /******************** TIM Instances : Advanced-control timers *****************/
27598 /********************* UART Instances : Half-Duplex mode **********************/
27630 /****************** UART Instances : Wake-up from Stop mode *******************/