Lines Matching refs:tmpccer

561   uint32_t tmpccer;  in LL_TIM_ENCODER_Init()  local
582 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_ENCODER_Init()
597 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_ENCODER_Init()
598 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); in LL_TIM_ENCODER_Init()
599 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); in LL_TIM_ENCODER_Init()
600 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_ENCODER_Init()
609 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_ENCODER_Init()
655 uint32_t tmpccer; in LL_TIM_HALLSENSOR_Init() local
674 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_HALLSENSOR_Init()
701 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_HALLSENSOR_Init()
702 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); in LL_TIM_HALLSENSOR_Init()
703 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_HALLSENSOR_Init()
715 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_HALLSENSOR_Init()
848 uint32_t tmpccer; in OC1Config() local
861 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC1Config()
876 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); in OC1Config()
879 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
889 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); in OC1Config()
892 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
911 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC1Config()
927 uint32_t tmpccer; in OC2Config() local
940 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC2Config()
955 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); in OC2Config()
958 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
968 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); in OC2Config()
971 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
990 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC2Config()
1006 uint32_t tmpccer; in OC3Config() local
1019 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC3Config()
1034 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); in OC3Config()
1037 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1047 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); in OC3Config()
1050 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1069 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC3Config()
1085 uint32_t tmpccer; in OC4Config() local
1098 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC4Config()
1113 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); in OC4Config()
1116 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1136 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC4Config()
1152 uint32_t tmpccer; in OC5Config() local
1166 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC5Config()
1175 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); in OC5Config()
1178 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); in OC5Config()
1197 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC5Config()
1213 uint32_t tmpccer; in OC6Config() local
1227 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC6Config()
1236 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); in OC6Config()
1239 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); in OC6Config()
1257 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC6Config()