576   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
582   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
609   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
665   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
674   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
715   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
858   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
861   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
911   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
937   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
940   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
990   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
1016   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
1019   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
1069   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1095   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1098   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1136   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1163   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1166   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1197   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1224   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1227   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1257   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1280   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1288   MODIFY_REG(TIMx->CCER,  in IC1Config()
1313   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1321   MODIFY_REG(TIMx->CCER,  in IC2Config()
1346   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1354   MODIFY_REG(TIMx->CCER,  in IC3Config()
1379   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1387   MODIFY_REG(TIMx->CCER,  in IC4Config()