Lines Matching refs:htim
227 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
269 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Init() argument
272 if (htim == NULL) in HAL_TIM_Base_Init()
278 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Init()
279 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_Base_Init()
280 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_Base_Init()
281 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_Base_Init()
282 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_Base_Init()
284 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_Base_Init()
287 htim->Lock = HAL_UNLOCKED; in HAL_TIM_Base_Init()
291 TIM_ResetCallback(htim); in HAL_TIM_Base_Init()
293 if (htim->Base_MspInitCallback == NULL) in HAL_TIM_Base_Init()
295 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_Base_Init()
298 htim->Base_MspInitCallback(htim); in HAL_TIM_Base_Init()
301 HAL_TIM_Base_MspInit(htim); in HAL_TIM_Base_Init()
306 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Init()
309 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_Base_Init()
312 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_Base_Init()
315 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Base_Init()
316 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Base_Init()
319 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Init()
329 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_DeInit() argument
332 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_DeInit()
334 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_DeInit()
337 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_DeInit()
340 if (htim->Base_MspDeInitCallback == NULL) in HAL_TIM_Base_DeInit()
342 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_Base_DeInit()
345 htim->Base_MspDeInitCallback(htim); in HAL_TIM_Base_DeInit()
348 HAL_TIM_Base_MspDeInit(htim); in HAL_TIM_Base_DeInit()
352 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_Base_DeInit()
355 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Base_DeInit()
356 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Base_DeInit()
359 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_Base_DeInit()
362 __HAL_UNLOCK(htim); in HAL_TIM_Base_DeInit()
372 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_MspInit() argument
375 UNUSED(htim); in HAL_TIM_Base_MspInit()
387 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_MspDeInit() argument
390 UNUSED(htim); in HAL_TIM_Base_MspDeInit()
403 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Start() argument
408 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start()
411 if (htim->State != HAL_TIM_STATE_READY) in HAL_TIM_Base_Start()
417 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start()
420 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start()
422 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start()
425 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start()
430 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start()
442 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop() argument
445 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop()
448 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop()
451 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop()
462 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Start_IT() argument
467 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start_IT()
470 if (htim->State != HAL_TIM_STATE_READY) in HAL_TIM_Base_Start_IT()
476 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start_IT()
479 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); in HAL_TIM_Base_Start_IT()
482 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start_IT()
484 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start_IT()
487 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_IT()
492 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_IT()
504 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop_IT() argument
507 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop_IT()
510 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); in HAL_TIM_Base_Stop_IT()
513 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop_IT()
516 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop_IT()
529 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t L… in HAL_TIM_Base_Start_DMA() argument
534 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start_DMA()
537 if (htim->State == HAL_TIM_STATE_BUSY) in HAL_TIM_Base_Start_DMA()
541 else if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_Base_Start_DMA()
549 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start_DMA()
558 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_Base_Start_DMA()
559 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_Base_Start_DMA()
562 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Base_Start_DMA()
565 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->AR… in HAL_TIM_Base_Start_DMA()
573 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); in HAL_TIM_Base_Start_DMA()
576 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start_DMA()
578 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start_DMA()
581 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_DMA()
586 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_DMA()
598 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop_DMA() argument
601 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop_DMA()
604 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); in HAL_TIM_Base_Stop_DMA()
606 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_Base_Stop_DMA()
609 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop_DMA()
612 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop_DMA()
653 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) in HAL_TIM_OC_Init() argument
656 if (htim == NULL) in HAL_TIM_OC_Init()
662 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OC_Init()
663 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_OC_Init()
664 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_OC_Init()
665 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_OC_Init()
666 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_OC_Init()
668 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_OC_Init()
671 htim->Lock = HAL_UNLOCKED; in HAL_TIM_OC_Init()
675 TIM_ResetCallback(htim); in HAL_TIM_OC_Init()
677 if (htim->OC_MspInitCallback == NULL) in HAL_TIM_OC_Init()
679 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_OC_Init()
682 htim->OC_MspInitCallback(htim); in HAL_TIM_OC_Init()
685 HAL_TIM_OC_MspInit(htim); in HAL_TIM_OC_Init()
690 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OC_Init()
693 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_OC_Init()
696 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_OC_Init()
699 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Init()
700 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Init()
703 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OC_Init()
713 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_DeInit() argument
716 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OC_DeInit()
718 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OC_DeInit()
721 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_DeInit()
724 if (htim->OC_MspDeInitCallback == NULL) in HAL_TIM_OC_DeInit()
726 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_OC_DeInit()
729 htim->OC_MspDeInitCallback(htim); in HAL_TIM_OC_DeInit()
732 HAL_TIM_OC_MspDeInit(htim); in HAL_TIM_OC_DeInit()
736 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_OC_DeInit()
739 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OC_DeInit()
740 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OC_DeInit()
743 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_OC_DeInit()
746 __HAL_UNLOCK(htim); in HAL_TIM_OC_DeInit()
756 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_MspInit() argument
759 UNUSED(htim); in HAL_TIM_OC_MspInit()
771 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_MspDeInit() argument
774 UNUSED(htim); in HAL_TIM_OC_MspDeInit()
794 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Start() argument
799 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_OC_Start()
802 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start()
808 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start()
811 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start()
813 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start()
816 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start()
820 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start()
822 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start()
825 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start()
830 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start()
850 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop() argument
853 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_OC_Stop()
856 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop()
858 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop()
861 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop()
865 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop()
868 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop()
885 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Start_IT() argument
891 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Start_IT()
894 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start_IT()
900 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start_IT()
907 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OC_Start_IT()
914 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OC_Start_IT()
921 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_OC_Start_IT()
928 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_OC_Start_IT()
940 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start_IT()
942 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start_IT()
945 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start_IT()
949 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start_IT()
951 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start_IT()
954 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_IT()
959 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_IT()
978 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop_IT() argument
983 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Stop_IT()
990 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OC_Stop_IT()
997 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OC_Stop_IT()
1004 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_OC_Stop_IT()
1011 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_OC_Stop_IT()
1023 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop_IT()
1025 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop_IT()
1028 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop_IT()
1032 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop_IT()
1035 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop_IT()
1055 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *p… in HAL_TIM_OC_Start_DMA() argument
1062 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Start_DMA()
1065 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) in HAL_TIM_OC_Start_DMA()
1069 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start_DMA()
1077 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start_DMA()
1090 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1091 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1094 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1097 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, in HAL_TIM_OC_Start_DMA()
1105 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_OC_Start_DMA()
1112 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1113 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1116 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1119 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, in HAL_TIM_OC_Start_DMA()
1127 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_OC_Start_DMA()
1134 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1135 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1138 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1141 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, in HAL_TIM_OC_Start_DMA()
1148 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_OC_Start_DMA()
1155 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1156 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1159 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1162 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, in HAL_TIM_OC_Start_DMA()
1169 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_OC_Start_DMA()
1181 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start_DMA()
1183 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start_DMA()
1186 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1190 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start_DMA()
1192 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start_DMA()
1195 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1200 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1219 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop_DMA() argument
1224 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Stop_DMA()
1231 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_OC_Stop_DMA()
1232 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_OC_Stop_DMA()
1239 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_OC_Stop_DMA()
1240 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_OC_Stop_DMA()
1247 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_OC_Stop_DMA()
1248 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_OC_Stop_DMA()
1255 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_OC_Stop_DMA()
1256 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_OC_Stop_DMA()
1268 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop_DMA()
1270 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop_DMA()
1273 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop_DMA()
1277 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop_DMA()
1280 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop_DMA()
1322 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_Init() argument
1325 if (htim == NULL) in HAL_TIM_PWM_Init()
1331 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_PWM_Init()
1332 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_PWM_Init()
1333 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_PWM_Init()
1334 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_PWM_Init()
1335 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_PWM_Init()
1337 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_PWM_Init()
1340 htim->Lock = HAL_UNLOCKED; in HAL_TIM_PWM_Init()
1344 TIM_ResetCallback(htim); in HAL_TIM_PWM_Init()
1346 if (htim->PWM_MspInitCallback == NULL) in HAL_TIM_PWM_Init()
1348 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_PWM_Init()
1351 htim->PWM_MspInitCallback(htim); in HAL_TIM_PWM_Init()
1354 HAL_TIM_PWM_MspInit(htim); in HAL_TIM_PWM_Init()
1359 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_PWM_Init()
1362 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_PWM_Init()
1365 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_PWM_Init()
1368 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Init()
1369 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Init()
1372 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_PWM_Init()
1382 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_DeInit() argument
1385 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_PWM_DeInit()
1387 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_PWM_DeInit()
1390 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_DeInit()
1393 if (htim->PWM_MspDeInitCallback == NULL) in HAL_TIM_PWM_DeInit()
1395 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_PWM_DeInit()
1398 htim->PWM_MspDeInitCallback(htim); in HAL_TIM_PWM_DeInit()
1401 HAL_TIM_PWM_MspDeInit(htim); in HAL_TIM_PWM_DeInit()
1405 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_PWM_DeInit()
1408 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_PWM_DeInit()
1409 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_PWM_DeInit()
1412 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_PWM_DeInit()
1415 __HAL_UNLOCK(htim); in HAL_TIM_PWM_DeInit()
1425 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_MspInit() argument
1428 UNUSED(htim); in HAL_TIM_PWM_MspInit()
1440 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_MspDeInit() argument
1443 UNUSED(htim); in HAL_TIM_PWM_MspDeInit()
1463 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Start() argument
1468 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_PWM_Start()
1471 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start()
1477 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start()
1480 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start()
1482 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start()
1485 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start()
1489 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start()
1491 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start()
1494 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start()
1499 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start()
1519 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop() argument
1522 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_PWM_Stop()
1525 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop()
1527 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop()
1530 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop()
1534 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop()
1537 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop()
1554 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Start_IT() argument
1560 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Start_IT()
1563 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start_IT()
1569 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start_IT()
1576 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_PWM_Start_IT()
1583 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_PWM_Start_IT()
1590 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_PWM_Start_IT()
1597 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_PWM_Start_IT()
1609 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start_IT()
1611 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start_IT()
1614 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1618 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start_IT()
1620 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start_IT()
1623 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1628 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1647 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop_IT() argument
1652 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Stop_IT()
1659 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_PWM_Stop_IT()
1666 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_PWM_Stop_IT()
1673 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_PWM_Stop_IT()
1680 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_PWM_Stop_IT()
1692 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop_IT()
1694 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop_IT()
1697 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop_IT()
1701 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop_IT()
1704 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop_IT()
1724 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *… in HAL_TIM_PWM_Start_DMA() argument
1731 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Start_DMA()
1734 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) in HAL_TIM_PWM_Start_DMA()
1738 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start_DMA()
1746 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start_DMA()
1759 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1760 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1763 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1766 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, in HAL_TIM_PWM_Start_DMA()
1774 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_PWM_Start_DMA()
1781 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1782 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1785 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1788 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, in HAL_TIM_PWM_Start_DMA()
1795 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_PWM_Start_DMA()
1802 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1803 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1806 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1809 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, in HAL_TIM_PWM_Start_DMA()
1816 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_PWM_Start_DMA()
1823 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1824 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1827 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1830 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, in HAL_TIM_PWM_Start_DMA()
1837 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_PWM_Start_DMA()
1849 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start_DMA()
1851 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start_DMA()
1854 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1858 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start_DMA()
1860 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start_DMA()
1863 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1868 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1887 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop_DMA() argument
1892 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Stop_DMA()
1899 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_PWM_Stop_DMA()
1900 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_PWM_Stop_DMA()
1907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_PWM_Stop_DMA()
1908 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_PWM_Stop_DMA()
1915 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_PWM_Stop_DMA()
1916 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_PWM_Stop_DMA()
1923 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_PWM_Stop_DMA()
1924 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_PWM_Stop_DMA()
1936 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop_DMA()
1938 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop_DMA()
1941 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop_DMA()
1945 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop_DMA()
1948 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop_DMA()
1990 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) in HAL_TIM_IC_Init() argument
1993 if (htim == NULL) in HAL_TIM_IC_Init()
1999 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_IC_Init()
2000 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_IC_Init()
2001 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_IC_Init()
2002 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_IC_Init()
2003 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_IC_Init()
2005 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_IC_Init()
2008 htim->Lock = HAL_UNLOCKED; in HAL_TIM_IC_Init()
2012 TIM_ResetCallback(htim); in HAL_TIM_IC_Init()
2014 if (htim->IC_MspInitCallback == NULL) in HAL_TIM_IC_Init()
2016 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_IC_Init()
2019 htim->IC_MspInitCallback(htim); in HAL_TIM_IC_Init()
2022 HAL_TIM_IC_MspInit(htim); in HAL_TIM_IC_Init()
2027 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_IC_Init()
2030 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_IC_Init()
2033 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_IC_Init()
2036 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Init()
2037 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Init()
2040 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_IC_Init()
2050 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_DeInit() argument
2053 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_IC_DeInit()
2055 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_IC_DeInit()
2058 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_DeInit()
2061 if (htim->IC_MspDeInitCallback == NULL) in HAL_TIM_IC_DeInit()
2063 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_IC_DeInit()
2066 htim->IC_MspDeInitCallback(htim); in HAL_TIM_IC_DeInit()
2069 HAL_TIM_IC_MspDeInit(htim); in HAL_TIM_IC_DeInit()
2073 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_IC_DeInit()
2076 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_IC_DeInit()
2077 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_IC_DeInit()
2080 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_IC_DeInit()
2083 __HAL_UNLOCK(htim); in HAL_TIM_IC_DeInit()
2093 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_MspInit() argument
2096 UNUSED(htim); in HAL_TIM_IC_MspInit()
2108 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_MspDeInit() argument
2111 UNUSED(htim); in HAL_TIM_IC_MspDeInit()
2129 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Start() argument
2132 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start()
2133 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start()
2136 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start()
2146 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start()
2147 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start()
2150 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start()
2153 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start()
2155 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start()
2158 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start()
2163 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start()
2181 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop() argument
2184 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop()
2187 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop()
2190 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop()
2193 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop()
2194 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop()
2211 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Start_IT() argument
2216 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_IT()
2217 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_IT()
2220 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start_IT()
2230 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_IT()
2231 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_IT()
2238 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_IC_Start_IT()
2245 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_IC_Start_IT()
2252 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_IC_Start_IT()
2259 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_IC_Start_IT()
2271 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start_IT()
2274 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start_IT()
2276 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start_IT()
2279 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_IT()
2284 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_IT()
2303 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop_IT() argument
2308 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop_IT()
2315 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_IC_Stop_IT()
2322 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_IC_Stop_IT()
2329 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_IC_Stop_IT()
2336 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_IC_Stop_IT()
2348 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop_IT()
2351 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop_IT()
2354 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_IT()
2355 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_IT()
2375 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, … in HAL_TIM_IC_Start_DMA() argument
2380 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_DMA()
2381 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_DMA()
2384 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start_DMA()
2385 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); in HAL_TIM_IC_Start_DMA()
2402 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_DMA()
2403 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_DMA()
2412 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start_DMA()
2419 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2420 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2423 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2426 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2433 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_IC_Start_DMA()
2440 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2441 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2444 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2447 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2454 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_IC_Start_DMA()
2461 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2462 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2465 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2468 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2475 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_IC_Start_DMA()
2482 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2483 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2486 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2489 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2496 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_IC_Start_DMA()
2506 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start_DMA()
2508 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start_DMA()
2511 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_DMA()
2516 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_DMA()
2534 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop_DMA() argument
2539 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop_DMA()
2540 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); in HAL_TIM_IC_Stop_DMA()
2543 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop_DMA()
2550 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_IC_Stop_DMA()
2551 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_IC_Stop_DMA()
2558 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_IC_Stop_DMA()
2559 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_IC_Stop_DMA()
2566 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_IC_Stop_DMA()
2567 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_IC_Stop_DMA()
2574 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_IC_Stop_DMA()
2575 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_IC_Stop_DMA()
2587 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop_DMA()
2590 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_DMA()
2591 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_DMA()
2639 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) in HAL_TIM_OnePulse_Init() argument
2642 if (htim == NULL) in HAL_TIM_OnePulse_Init()
2648 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_Init()
2649 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_OnePulse_Init()
2650 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_OnePulse_Init()
2652 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_OnePulse_Init()
2653 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_OnePulse_Init()
2655 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_OnePulse_Init()
2658 htim->Lock = HAL_UNLOCKED; in HAL_TIM_OnePulse_Init()
2662 TIM_ResetCallback(htim); in HAL_TIM_OnePulse_Init()
2664 if (htim->OnePulse_MspInitCallback == NULL) in HAL_TIM_OnePulse_Init()
2666 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_OnePulse_Init()
2669 htim->OnePulse_MspInitCallback(htim); in HAL_TIM_OnePulse_Init()
2672 HAL_TIM_OnePulse_MspInit(htim); in HAL_TIM_OnePulse_Init()
2677 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_Init()
2680 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_OnePulse_Init()
2683 htim->Instance->CR1 &= ~TIM_CR1_OPM; in HAL_TIM_OnePulse_Init()
2686 htim->Instance->CR1 |= OnePulseMode; in HAL_TIM_OnePulse_Init()
2689 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_OnePulse_Init()
2692 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2693 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2694 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2695 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2698 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OnePulse_Init()
2708 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_DeInit() argument
2711 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_DeInit()
2713 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_DeInit()
2716 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_DeInit()
2719 if (htim->OnePulse_MspDeInitCallback == NULL) in HAL_TIM_OnePulse_DeInit()
2721 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_OnePulse_DeInit()
2724 htim->OnePulse_MspDeInitCallback(htim); in HAL_TIM_OnePulse_DeInit()
2727 HAL_TIM_OnePulse_MspDeInit(htim); in HAL_TIM_OnePulse_DeInit()
2731 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_OnePulse_DeInit()
2734 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2735 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2736 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2737 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2740 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_OnePulse_DeInit()
2743 __HAL_UNLOCK(htim); in HAL_TIM_OnePulse_DeInit()
2753 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_MspInit() argument
2756 UNUSED(htim); in HAL_TIM_OnePulse_MspInit()
2768 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_MspDeInit() argument
2771 UNUSED(htim); in HAL_TIM_OnePulse_MspDeInit()
2788 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Start() argument
2790 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_OnePulse_Start()
2791 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_OnePulse_Start()
2792 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start()
2793 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start()
2808 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2809 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2810 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2811 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2822 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start()
2823 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start()
2825 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Start()
2828 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OnePulse_Start()
2845 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Stop() argument
2856 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop()
2857 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop()
2859 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Stop()
2862 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OnePulse_Stop()
2866 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_Stop()
2869 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2870 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2871 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2872 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2888 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Start_IT() argument
2890 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_OnePulse_Start_IT()
2891 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_OnePulse_Start_IT()
2892 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start_IT()
2893 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start_IT()
2908 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2909 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2910 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2911 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2923 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OnePulse_Start_IT()
2926 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OnePulse_Start_IT()
2928 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start_IT()
2929 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start_IT()
2931 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Start_IT()
2934 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OnePulse_Start_IT()
2951 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Stop_IT() argument
2957 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OnePulse_Stop_IT()
2960 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OnePulse_Stop_IT()
2967 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop_IT()
2968 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop_IT()
2970 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Stop_IT()
2973 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OnePulse_Stop_IT()
2977 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_Stop_IT()
2980 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
2981 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
2982 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
2983 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
3030 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sCon… in HAL_TIM_Encoder_Init() argument
3037 if (htim == NULL) in HAL_TIM_Encoder_Init()
3043 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Init()
3044 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_Encoder_Init()
3045 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_Encoder_Init()
3046 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_Encoder_Init()
3056 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_Encoder_Init()
3058 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_Encoder_Init()
3061 htim->Lock = HAL_UNLOCKED; in HAL_TIM_Encoder_Init()
3065 TIM_ResetCallback(htim); in HAL_TIM_Encoder_Init()
3067 if (htim->Encoder_MspInitCallback == NULL) in HAL_TIM_Encoder_Init()
3069 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_Encoder_Init()
3072 htim->Encoder_MspInitCallback(htim); in HAL_TIM_Encoder_Init()
3075 HAL_TIM_Encoder_MspInit(htim); in HAL_TIM_Encoder_Init()
3080 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Encoder_Init()
3083 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); in HAL_TIM_Encoder_Init()
3086 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_Encoder_Init()
3089 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_Encoder_Init()
3092 tmpccmr1 = htim->Instance->CCMR1; in HAL_TIM_Encoder_Init()
3095 tmpccer = htim->Instance->CCER; in HAL_TIM_Encoder_Init()
3116 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_Encoder_Init()
3119 htim->Instance->CCMR1 = tmpccmr1; in HAL_TIM_Encoder_Init()
3122 htim->Instance->CCER = tmpccer; in HAL_TIM_Encoder_Init()
3125 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_Encoder_Init()
3128 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3129 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3130 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3131 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3134 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Encoder_Init()
3145 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_DeInit() argument
3148 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_DeInit()
3150 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Encoder_DeInit()
3153 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_DeInit()
3156 if (htim->Encoder_MspDeInitCallback == NULL) in HAL_TIM_Encoder_DeInit()
3158 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_Encoder_DeInit()
3161 htim->Encoder_MspDeInitCallback(htim); in HAL_TIM_Encoder_DeInit()
3164 HAL_TIM_Encoder_MspDeInit(htim); in HAL_TIM_Encoder_DeInit()
3168 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_Encoder_DeInit()
3171 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3172 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3173 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3174 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3177 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_Encoder_DeInit()
3180 __HAL_UNLOCK(htim); in HAL_TIM_Encoder_DeInit()
3190 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_MspInit() argument
3193 UNUSED(htim); in HAL_TIM_Encoder_MspInit()
3205 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_MspDeInit() argument
3208 UNUSED(htim); in HAL_TIM_Encoder_MspDeInit()
3225 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Start() argument
3227 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start()
3228 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start()
3229 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start()
3230 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start()
3233 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start()
3245 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3246 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3258 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3259 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3273 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3274 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3275 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3276 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3285 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3291 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3297 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3298 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3303 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start()
3319 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop() argument
3322 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop()
3330 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3336 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3342 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3343 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3349 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop()
3354 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3355 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3359 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3360 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3361 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3362 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3379 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Start_IT() argument
3381 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start_IT()
3382 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start_IT()
3383 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_IT()
3384 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_IT()
3387 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start_IT()
3399 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3400 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3412 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3413 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3427 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3428 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3429 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3430 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3440 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3441 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Start_IT()
3447 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3448 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Start_IT()
3454 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3455 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3456 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Start_IT()
3457 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Start_IT()
3463 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_IT()
3479 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop_IT() argument
3482 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop_IT()
3488 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3491 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Stop_IT()
3495 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3498 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Stop_IT()
3502 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3503 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3506 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Stop_IT()
3507 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Stop_IT()
3511 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop_IT()
3516 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3517 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3521 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3522 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3523 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3524 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3544 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pD… in HAL_TIM_Encoder_Start_DMA() argument
3547 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start_DMA()
3548 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start_DMA()
3549 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_DMA()
3550 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_DMA()
3553 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start_DMA()
3572 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3573 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3597 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3598 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3626 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3627 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3628 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3629 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3643 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3644 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3647 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3650 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, in HAL_TIM_Encoder_Start_DMA()
3657 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Start_DMA()
3660 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3663 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3671 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3672 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3675 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; in HAL_TIM_Encoder_Start_DMA()
3677 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, in HAL_TIM_Encoder_Start_DMA()
3684 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Start_DMA()
3687 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3690 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3698 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3699 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3702 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3705 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, in HAL_TIM_Encoder_Start_DMA()
3713 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3714 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3717 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3720 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, in HAL_TIM_Encoder_Start_DMA()
3728 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Start_DMA()
3730 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Start_DMA()
3733 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3734 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3737 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3757 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop_DMA() argument
3760 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop_DMA()
3766 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3769 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Stop_DMA()
3770 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_Encoder_Stop_DMA()
3774 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3777 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Stop_DMA()
3778 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_Encoder_Stop_DMA()
3782 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3783 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3786 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Stop_DMA()
3787 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Stop_DMA()
3788 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_Encoder_Stop_DMA()
3789 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_Encoder_Stop_DMA()
3793 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop_DMA()
3798 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3799 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3803 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3804 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3805 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3806 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3834 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) in HAL_TIM_IRQHandler() argument
3836 uint32_t itsource = htim->Instance->DIER; in HAL_TIM_IRQHandler()
3837 uint32_t itflag = htim->Instance->SR; in HAL_TIM_IRQHandler()
3845 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); in HAL_TIM_IRQHandler()
3846 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in HAL_TIM_IRQHandler()
3849 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) in HAL_TIM_IRQHandler()
3852 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3854 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3861 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3862 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3864 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3865 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3868 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3877 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); in HAL_TIM_IRQHandler()
3878 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in HAL_TIM_IRQHandler()
3880 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) in HAL_TIM_IRQHandler()
3883 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3885 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3892 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3893 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3895 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3896 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3899 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3907 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); in HAL_TIM_IRQHandler()
3908 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in HAL_TIM_IRQHandler()
3910 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) in HAL_TIM_IRQHandler()
3913 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3915 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3922 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3923 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3925 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3926 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3929 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3937 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); in HAL_TIM_IRQHandler()
3938 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in HAL_TIM_IRQHandler()
3940 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) in HAL_TIM_IRQHandler()
3943 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3945 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3952 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3953 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3955 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3956 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3959 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3967 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); in HAL_TIM_IRQHandler()
3969 htim->PeriodElapsedCallback(htim); in HAL_TIM_IRQHandler()
3971 HAL_TIM_PeriodElapsedCallback(htim); in HAL_TIM_IRQHandler()
3981 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); in HAL_TIM_IRQHandler()
3983 htim->BreakCallback(htim); in HAL_TIM_IRQHandler()
3985 HAL_TIMEx_BreakCallback(htim); in HAL_TIM_IRQHandler()
3994 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); in HAL_TIM_IRQHandler()
3996 htim->Break2Callback(htim); in HAL_TIM_IRQHandler()
3998 HAL_TIMEx_Break2Callback(htim); in HAL_TIM_IRQHandler()
4007 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); in HAL_TIM_IRQHandler()
4009 htim->TriggerCallback(htim); in HAL_TIM_IRQHandler()
4011 HAL_TIM_TriggerCallback(htim); in HAL_TIM_IRQHandler()
4020 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); in HAL_TIM_IRQHandler()
4022 htim->CommutationCallback(htim); in HAL_TIM_IRQHandler()
4024 HAL_TIMEx_CommutCallback(htim); in HAL_TIM_IRQHandler()
4068 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, in HAL_TIM_OC_ConfigChannel() argument
4080 __HAL_LOCK(htim); in HAL_TIM_OC_ConfigChannel()
4087 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4090 TIM_OC1_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4097 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4100 TIM_OC2_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4107 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4110 TIM_OC3_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4117 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4120 TIM_OC4_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4127 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4130 TIM_OC5_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4137 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4140 TIM_OC6_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4149 __HAL_UNLOCK(htim); in HAL_TIM_OC_ConfigChannel()
4167 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConf… in HAL_TIM_IC_ConfigChannel() argument
4172 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4179 __HAL_LOCK(htim); in HAL_TIM_IC_ConfigChannel()
4184 TIM_TI1_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4190 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; in HAL_TIM_IC_ConfigChannel()
4193 htim->Instance->CCMR1 |= sConfig->ICPrescaler; in HAL_TIM_IC_ConfigChannel()
4198 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4200 TIM_TI2_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4206 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; in HAL_TIM_IC_ConfigChannel()
4209 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); in HAL_TIM_IC_ConfigChannel()
4214 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4216 TIM_TI3_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4222 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; in HAL_TIM_IC_ConfigChannel()
4225 htim->Instance->CCMR2 |= sConfig->ICPrescaler; in HAL_TIM_IC_ConfigChannel()
4230 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4232 TIM_TI4_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4238 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; in HAL_TIM_IC_ConfigChannel()
4241 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); in HAL_TIM_IC_ConfigChannel()
4248 __HAL_UNLOCK(htim); in HAL_TIM_IC_ConfigChannel()
4268 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, in HAL_TIM_PWM_ConfigChannel() argument
4281 __HAL_LOCK(htim); in HAL_TIM_PWM_ConfigChannel()
4288 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4291 TIM_OC1_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4294 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; in HAL_TIM_PWM_ConfigChannel()
4297 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; in HAL_TIM_PWM_ConfigChannel()
4298 htim->Instance->CCMR1 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4305 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4308 TIM_OC2_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4311 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; in HAL_TIM_PWM_ConfigChannel()
4314 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; in HAL_TIM_PWM_ConfigChannel()
4315 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4322 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4325 TIM_OC3_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4328 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; in HAL_TIM_PWM_ConfigChannel()
4331 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; in HAL_TIM_PWM_ConfigChannel()
4332 htim->Instance->CCMR2 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4339 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4342 TIM_OC4_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4345 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; in HAL_TIM_PWM_ConfigChannel()
4348 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; in HAL_TIM_PWM_ConfigChannel()
4349 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4356 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4359 TIM_OC5_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4362 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; in HAL_TIM_PWM_ConfigChannel()
4365 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; in HAL_TIM_PWM_ConfigChannel()
4366 htim->Instance->CCMR3 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4373 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4376 TIM_OC6_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4379 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; in HAL_TIM_PWM_ConfigChannel()
4382 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; in HAL_TIM_PWM_ConfigChannel()
4383 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4392 __HAL_UNLOCK(htim); in HAL_TIM_PWM_ConfigChannel()
4416 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef… in HAL_TIM_OnePulse_ConfigChannel() argument
4429 __HAL_LOCK(htim); in HAL_TIM_OnePulse_ConfigChannel()
4431 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_ConfigChannel()
4445 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4447 TIM_OC1_SetConfig(htim->Instance, &temp1); in HAL_TIM_OnePulse_ConfigChannel()
4453 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4455 TIM_OC2_SetConfig(htim->Instance, &temp1); in HAL_TIM_OnePulse_ConfigChannel()
4470 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4472 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, in HAL_TIM_OnePulse_ConfigChannel()
4476 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; in HAL_TIM_OnePulse_ConfigChannel()
4479 htim->Instance->SMCR &= ~TIM_SMCR_TS; in HAL_TIM_OnePulse_ConfigChannel()
4480 htim->Instance->SMCR |= TIM_TS_TI1FP1; in HAL_TIM_OnePulse_ConfigChannel()
4483 htim->Instance->SMCR &= ~TIM_SMCR_SMS; in HAL_TIM_OnePulse_ConfigChannel()
4484 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; in HAL_TIM_OnePulse_ConfigChannel()
4490 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4492 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, in HAL_TIM_OnePulse_ConfigChannel()
4496 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; in HAL_TIM_OnePulse_ConfigChannel()
4499 htim->Instance->SMCR &= ~TIM_SMCR_TS; in HAL_TIM_OnePulse_ConfigChannel()
4500 htim->Instance->SMCR |= TIM_TS_TI2FP2; in HAL_TIM_OnePulse_ConfigChannel()
4503 htim->Instance->SMCR &= ~TIM_SMCR_SMS; in HAL_TIM_OnePulse_ConfigChannel()
4504 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; in HAL_TIM_OnePulse_ConfigChannel()
4514 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OnePulse_ConfigChannel()
4516 __HAL_UNLOCK(htim); in HAL_TIM_OnePulse_ConfigChannel()
4571 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, in HAL_TIM_DMABurst_WriteStart() argument
4577 …status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bu… in HAL_TIM_DMABurst_WriteStart()
4631 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddre… in HAL_TIM_DMABurst_MultiWriteStart() argument
4638 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurst_MultiWriteStart()
4644 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) in HAL_TIM_DMABurst_MultiWriteStart()
4648 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) in HAL_TIM_DMABurst_MultiWriteStart()
4656 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; in HAL_TIM_DMABurst_MultiWriteStart()
4669 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4670 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4673 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4676 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4677 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4687 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4688 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4691 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4694 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4695 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4705 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4706 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4709 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4712 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4713 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4723 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4724 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4727 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4730 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4731 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4741 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4742 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4745 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4748 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4749 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4759 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4760 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4763 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4766 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4767 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4777 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4778 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4781 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4784 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4785 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4800 htim->Instance->DCR = (BurstBaseAddress | BurstLength); in HAL_TIM_DMABurst_MultiWriteStart()
4802 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_MultiWriteStart()
4815 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) in HAL_TIM_DMABurst_WriteStop() argument
4827 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_DMABurst_WriteStop()
4832 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_DMABurst_WriteStop()
4837 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_DMABurst_WriteStop()
4842 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_DMABurst_WriteStop()
4847 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_DMABurst_WriteStop()
4852 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); in HAL_TIM_DMABurst_WriteStop()
4857 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); in HAL_TIM_DMABurst_WriteStop()
4868 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_WriteStop()
4871 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_DMABurst_WriteStop()
4923 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, in HAL_TIM_DMABurst_ReadStart() argument
4928 …status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bur… in HAL_TIM_DMABurst_ReadStart()
4981 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddres… in HAL_TIM_DMABurst_MultiReadStart() argument
4988 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurst_MultiReadStart()
4994 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) in HAL_TIM_DMABurst_MultiReadStart()
4998 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) in HAL_TIM_DMABurst_MultiReadStart()
5006 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; in HAL_TIM_DMABurst_MultiReadStart()
5018 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_DMABurst_MultiReadStart()
5019 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5022 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5025 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)Bur… in HAL_TIM_DMABurst_MultiReadStart()
5036 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5037 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5040 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5043 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5054 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5055 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5058 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5061 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5072 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5073 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5076 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5079 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5090 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5091 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5094 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5097 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5108 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; in HAL_TIM_DMABurst_MultiReadStart()
5109 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5112 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5115 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_… in HAL_TIM_DMABurst_MultiReadStart()
5126 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; in HAL_TIM_DMABurst_MultiReadStart()
5127 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5130 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5133 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)Bu… in HAL_TIM_DMABurst_MultiReadStart()
5149 htim->Instance->DCR = (BurstBaseAddress | BurstLength); in HAL_TIM_DMABurst_MultiReadStart()
5152 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_MultiReadStart()
5165 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) in HAL_TIM_DMABurst_ReadStop() argument
5177 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_DMABurst_ReadStop()
5182 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_DMABurst_ReadStop()
5187 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_DMABurst_ReadStop()
5192 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_DMABurst_ReadStop()
5197 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_DMABurst_ReadStop()
5202 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); in HAL_TIM_DMABurst_ReadStop()
5207 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); in HAL_TIM_DMABurst_ReadStop()
5218 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_ReadStop()
5221 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_DMABurst_ReadStop()
5249 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) in HAL_TIM_GenerateEvent() argument
5252 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_GenerateEvent()
5256 __HAL_LOCK(htim); in HAL_TIM_GenerateEvent()
5259 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_GenerateEvent()
5262 htim->Instance->EGR = EventSource; in HAL_TIM_GenerateEvent()
5265 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_GenerateEvent()
5267 __HAL_UNLOCK(htim); in HAL_TIM_GenerateEvent()
5288 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, in HAL_TIM_ConfigOCrefClear() argument
5295 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); in HAL_TIM_ConfigOCrefClear()
5299 __HAL_LOCK(htim); in HAL_TIM_ConfigOCrefClear()
5301 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_ConfigOCrefClear()
5308 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); in HAL_TIM_ConfigOCrefClear()
5322 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigOCrefClear()
5323 __HAL_UNLOCK(htim); in HAL_TIM_ConfigOCrefClear()
5327 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigOCrefClear()
5348 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); in HAL_TIM_ConfigOCrefClear()
5353 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); in HAL_TIM_ConfigOCrefClear()
5362 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); in HAL_TIM_ConfigOCrefClear()
5367 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); in HAL_TIM_ConfigOCrefClear()
5376 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); in HAL_TIM_ConfigOCrefClear()
5381 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); in HAL_TIM_ConfigOCrefClear()
5390 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); in HAL_TIM_ConfigOCrefClear()
5395 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); in HAL_TIM_ConfigOCrefClear()
5404 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); in HAL_TIM_ConfigOCrefClear()
5409 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); in HAL_TIM_ConfigOCrefClear()
5418 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); in HAL_TIM_ConfigOCrefClear()
5423 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); in HAL_TIM_ConfigOCrefClear()
5432 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigOCrefClear()
5434 __HAL_UNLOCK(htim); in HAL_TIM_ConfigOCrefClear()
5446 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *… in HAL_TIM_ConfigClockSource() argument
5452 __HAL_LOCK(htim); in HAL_TIM_ConfigClockSource()
5454 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_ConfigClockSource()
5460 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_ConfigClockSource()
5463 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_ConfigClockSource()
5469 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5476 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5484 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigClockSource()
5490 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_ConfigClockSource()
5493 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_ConfigClockSource()
5500 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5508 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigClockSource()
5513 htim->Instance->SMCR |= TIM_SMCR_ECE; in HAL_TIM_ConfigClockSource()
5520 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5526 TIM_TI1_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5529 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); in HAL_TIM_ConfigClockSource()
5536 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5542 TIM_TI2_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5545 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); in HAL_TIM_ConfigClockSource()
5552 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5558 TIM_TI1_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5561 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); in HAL_TIM_ConfigClockSource()
5576 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5578 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); in HAL_TIM_ConfigClockSource()
5586 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigClockSource()
5588 __HAL_UNLOCK(htim); in HAL_TIM_ConfigClockSource()
5605 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) in HAL_TIM_ConfigTI1Input() argument
5610 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); in HAL_TIM_ConfigTI1Input()
5614 tmpcr2 = htim->Instance->CR2; in HAL_TIM_ConfigTI1Input()
5623 htim->Instance->CR2 = tmpcr2; in HAL_TIM_ConfigTI1Input()
5637 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef … in HAL_TIM_SlaveConfigSynchro() argument
5640 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); in HAL_TIM_SlaveConfigSynchro()
5644 __HAL_LOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5646 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_SlaveConfigSynchro()
5648 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) in HAL_TIM_SlaveConfigSynchro()
5650 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro()
5651 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5656 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); in HAL_TIM_SlaveConfigSynchro()
5659 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); in HAL_TIM_SlaveConfigSynchro()
5661 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro()
5663 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5677 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, in HAL_TIM_SlaveConfigSynchro_IT() argument
5681 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); in HAL_TIM_SlaveConfigSynchro_IT()
5685 __HAL_LOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5687 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_SlaveConfigSynchro_IT()
5689 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) in HAL_TIM_SlaveConfigSynchro_IT()
5691 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro_IT()
5692 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5697 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); in HAL_TIM_SlaveConfigSynchro_IT()
5700 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); in HAL_TIM_SlaveConfigSynchro_IT()
5702 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro_IT()
5704 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5720 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_ReadCapturedValue() argument
5729 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5732 tmpreg = htim->Instance->CCR1; in HAL_TIM_ReadCapturedValue()
5739 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5742 tmpreg = htim->Instance->CCR2; in HAL_TIM_ReadCapturedValue()
5750 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5753 tmpreg = htim->Instance->CCR3; in HAL_TIM_ReadCapturedValue()
5761 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5764 tmpreg = htim->Instance->CCR4; in HAL_TIM_ReadCapturedValue()
5804 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PeriodElapsedCallback() argument
5807 UNUSED(htim); in HAL_TIM_PeriodElapsedCallback()
5819 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PeriodElapsedHalfCpltCallback() argument
5822 UNUSED(htim); in HAL_TIM_PeriodElapsedHalfCpltCallback()
5834 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_OC_DelayElapsedCallback() argument
5837 UNUSED(htim); in HAL_TIM_OC_DelayElapsedCallback()
5849 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) in HAL_TIM_IC_CaptureCallback() argument
5852 UNUSED(htim); in HAL_TIM_IC_CaptureCallback()
5864 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_IC_CaptureHalfCpltCallback() argument
5867 UNUSED(htim); in HAL_TIM_IC_CaptureHalfCpltCallback()
5879 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_PulseFinishedCallback() argument
5882 UNUSED(htim); in HAL_TIM_PWM_PulseFinishedCallback()
5894 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_PulseFinishedHalfCpltCallback() argument
5897 UNUSED(htim); in HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
5909 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) in HAL_TIM_TriggerCallback() argument
5912 UNUSED(htim); in HAL_TIM_TriggerCallback()
5924 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_TriggerHalfCpltCallback() argument
5927 UNUSED(htim); in HAL_TIM_TriggerHalfCpltCallback()
5939 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) in HAL_TIM_ErrorCallback() argument
5942 UNUSED(htim); in HAL_TIM_ErrorCallback()
5986 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Callb… in HAL_TIM_RegisterCallback() argument
5996 if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_RegisterCallback()
6001 htim->Base_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6005 htim->Base_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6009 htim->IC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6013 htim->IC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6017 htim->OC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6021 htim->OC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6025 htim->PWM_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6029 htim->PWM_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6033 htim->OnePulse_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6037 htim->OnePulse_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6041 htim->Encoder_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6045 htim->Encoder_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6049 htim->HallSensor_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6053 htim->HallSensor_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6057 htim->PeriodElapsedCallback = pCallback; in HAL_TIM_RegisterCallback()
6061 htim->PeriodElapsedHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6065 htim->TriggerCallback = pCallback; in HAL_TIM_RegisterCallback()
6069 htim->TriggerHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6073 htim->IC_CaptureCallback = pCallback; in HAL_TIM_RegisterCallback()
6077 htim->IC_CaptureHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6081 htim->OC_DelayElapsedCallback = pCallback; in HAL_TIM_RegisterCallback()
6085 htim->PWM_PulseFinishedCallback = pCallback; in HAL_TIM_RegisterCallback()
6089 htim->PWM_PulseFinishedHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6093 htim->ErrorCallback = pCallback; in HAL_TIM_RegisterCallback()
6097 htim->CommutationCallback = pCallback; in HAL_TIM_RegisterCallback()
6101 htim->CommutationHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6105 htim->BreakCallback = pCallback; in HAL_TIM_RegisterCallback()
6109 htim->Break2Callback = pCallback; in HAL_TIM_RegisterCallback()
6118 else if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_RegisterCallback()
6123 htim->Base_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6127 htim->Base_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6131 htim->IC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6135 htim->IC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6139 htim->OC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6143 htim->OC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6147 htim->PWM_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6151 htim->PWM_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6155 htim->OnePulse_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6159 htim->OnePulse_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6163 htim->Encoder_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6167 htim->Encoder_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6171 htim->HallSensor_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6175 htim->HallSensor_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6229 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Cal… in HAL_TIM_UnRegisterCallback() argument
6233 if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_UnRegisterCallback()
6239 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_UnRegisterCallback()
6244 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_UnRegisterCallback()
6249 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_UnRegisterCallback()
6254 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6259 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_UnRegisterCallback()
6264 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6269 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_UnRegisterCallback()
6274 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_UnRegisterCallback()
6279 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_UnRegisterCallback()
6284 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_UnRegisterCallback()
6289 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_UnRegisterCallback()
6294 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_UnRegisterCallback()
6299 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; in HAL_TIM_UnRegisterCallback()
6304 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; in HAL_TIM_UnRegisterCallback()
6309 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; in HAL_TIM_UnRegisterCallback()
6314 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6319 htim->TriggerCallback = HAL_TIM_TriggerCallback; in HAL_TIM_UnRegisterCallback()
6324 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6329 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; in HAL_TIM_UnRegisterCallback()
6334 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6339 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; in HAL_TIM_UnRegisterCallback()
6344 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; in HAL_TIM_UnRegisterCallback()
6349 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6354 htim->ErrorCallback = HAL_TIM_ErrorCallback; in HAL_TIM_UnRegisterCallback()
6359 htim->CommutationCallback = HAL_TIMEx_CommutCallback; in HAL_TIM_UnRegisterCallback()
6364 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6369 htim->BreakCallback = HAL_TIMEx_BreakCallback; in HAL_TIM_UnRegisterCallback()
6374 htim->Break2Callback = HAL_TIMEx_Break2Callback; in HAL_TIM_UnRegisterCallback()
6383 else if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_UnRegisterCallback()
6389 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_UnRegisterCallback()
6394 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_UnRegisterCallback()
6399 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_UnRegisterCallback()
6404 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6409 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_UnRegisterCallback()
6414 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6419 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_UnRegisterCallback()
6424 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_UnRegisterCallback()
6429 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_UnRegisterCallback()
6434 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_UnRegisterCallback()
6439 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_UnRegisterCallback()
6444 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_UnRegisterCallback()
6449 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; in HAL_TIM_UnRegisterCallback()
6454 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; in HAL_TIM_UnRegisterCallback()
6497 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_Base_GetState() argument
6499 return htim->State; in HAL_TIM_Base_GetState()
6507 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_OC_GetState() argument
6509 return htim->State; in HAL_TIM_OC_GetState()
6517 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_PWM_GetState() argument
6519 return htim->State; in HAL_TIM_PWM_GetState()
6527 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_IC_GetState() argument
6529 return htim->State; in HAL_TIM_IC_GetState()
6537 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_GetState() argument
6539 return htim->State; in HAL_TIM_OnePulse_GetState()
6547 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_GetState() argument
6549 return htim->State; in HAL_TIM_Encoder_GetState()
6557 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) in HAL_TIM_GetActiveChannel() argument
6559 return htim->Channel; in HAL_TIM_GetActiveChannel()
6575 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channe… in HAL_TIM_GetChannelState() argument
6580 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_GetChannelState()
6582 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_GetChannelState()
6592 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) in HAL_TIM_DMABurstState() argument
6595 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurstState()
6597 return htim->DMABurstState; in HAL_TIM_DMABurstState()
6619 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAError() local
6621 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMAError()
6623 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMAError()
6624 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6626 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMAError()
6628 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMAError()
6629 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6631 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMAError()
6633 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMAError()
6634 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6636 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMAError()
6638 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMAError()
6639 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6643 htim->State = HAL_TIM_STATE_READY; in TIM_DMAError()
6647 htim->ErrorCallback(htim); in TIM_DMAError()
6649 HAL_TIM_ErrorCallback(htim); in TIM_DMAError()
6652 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMAError()
6662 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMADelayPulseCplt() local
6664 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMADelayPulseCplt()
6666 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMADelayPulseCplt()
6670 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6673 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMADelayPulseCplt()
6675 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMADelayPulseCplt()
6679 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6682 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMADelayPulseCplt()
6684 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMADelayPulseCplt()
6688 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6691 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMADelayPulseCplt()
6693 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMADelayPulseCplt()
6697 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6706 htim->PWM_PulseFinishedCallback(htim); in TIM_DMADelayPulseCplt()
6708 HAL_TIM_PWM_PulseFinishedCallback(htim); in TIM_DMADelayPulseCplt()
6711 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMADelayPulseCplt()
6721 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMADelayPulseHalfCplt() local
6723 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMADelayPulseHalfCplt()
6725 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMADelayPulseHalfCplt()
6727 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMADelayPulseHalfCplt()
6729 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMADelayPulseHalfCplt()
6731 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMADelayPulseHalfCplt()
6733 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMADelayPulseHalfCplt()
6735 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMADelayPulseHalfCplt()
6737 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMADelayPulseHalfCplt()
6745 htim->PWM_PulseFinishedHalfCpltCallback(htim); in TIM_DMADelayPulseHalfCplt()
6747 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); in TIM_DMADelayPulseHalfCplt()
6750 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMADelayPulseHalfCplt()
6760 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMACaptureCplt() local
6762 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMACaptureCplt()
6764 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMACaptureCplt()
6768 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6769 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6772 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMACaptureCplt()
6774 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMACaptureCplt()
6778 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6779 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6782 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMACaptureCplt()
6784 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMACaptureCplt()
6788 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6789 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6792 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMACaptureCplt()
6794 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMACaptureCplt()
6798 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6799 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6808 htim->IC_CaptureCallback(htim); in TIM_DMACaptureCplt()
6810 HAL_TIM_IC_CaptureCallback(htim); in TIM_DMACaptureCplt()
6813 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMACaptureCplt()
6823 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMACaptureHalfCplt() local
6825 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMACaptureHalfCplt()
6827 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMACaptureHalfCplt()
6829 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMACaptureHalfCplt()
6831 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMACaptureHalfCplt()
6833 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMACaptureHalfCplt()
6835 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMACaptureHalfCplt()
6837 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMACaptureHalfCplt()
6839 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMACaptureHalfCplt()
6847 htim->IC_CaptureHalfCpltCallback(htim); in TIM_DMACaptureHalfCplt()
6849 HAL_TIM_IC_CaptureHalfCpltCallback(htim); in TIM_DMACaptureHalfCplt()
6852 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMACaptureHalfCplt()
6862 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAPeriodElapsedCplt() local
6864 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) in TIM_DMAPeriodElapsedCplt()
6866 htim->State = HAL_TIM_STATE_READY; in TIM_DMAPeriodElapsedCplt()
6870 htim->PeriodElapsedCallback(htim); in TIM_DMAPeriodElapsedCplt()
6872 HAL_TIM_PeriodElapsedCallback(htim); in TIM_DMAPeriodElapsedCplt()
6883 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAPeriodElapsedHalfCplt() local
6886 htim->PeriodElapsedHalfCpltCallback(htim); in TIM_DMAPeriodElapsedHalfCplt()
6888 HAL_TIM_PeriodElapsedHalfCpltCallback(htim); in TIM_DMAPeriodElapsedHalfCplt()
6899 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMATriggerCplt() local
6901 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) in TIM_DMATriggerCplt()
6903 htim->State = HAL_TIM_STATE_READY; in TIM_DMATriggerCplt()
6907 htim->TriggerCallback(htim); in TIM_DMATriggerCplt()
6909 HAL_TIM_TriggerCallback(htim); in TIM_DMATriggerCplt()
6920 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMATriggerHalfCplt() local
6923 htim->TriggerHalfCpltCallback(htim); in TIM_DMATriggerHalfCplt()
6925 HAL_TIM_TriggerHalfCpltCallback(htim); in TIM_DMATriggerHalfCplt()
7384 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, in TIM_SlaveTimer_SetConfig() argument
7393 tmpsmcr = htim->Instance->SMCR; in TIM_SlaveTimer_SetConfig()
7406 htim->Instance->SMCR = tmpsmcr; in TIM_SlaveTimer_SetConfig()
7414 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7419 TIM_ETR_SetConfig(htim->Instance, in TIM_SlaveTimer_SetConfig()
7429 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7438 tmpccer = htim->Instance->CCER; in TIM_SlaveTimer_SetConfig()
7439 htim->Instance->CCER &= ~TIM_CCER_CC1E; in TIM_SlaveTimer_SetConfig()
7440 tmpccmr1 = htim->Instance->CCMR1; in TIM_SlaveTimer_SetConfig()
7447 htim->Instance->CCMR1 = tmpccmr1; in TIM_SlaveTimer_SetConfig()
7448 htim->Instance->CCER = tmpccer; in TIM_SlaveTimer_SetConfig()
7455 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7460 TIM_TI1_ConfigInputStage(htim->Instance, in TIM_SlaveTimer_SetConfig()
7469 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7474 TIM_TI2_ConfigInputStage(htim->Instance, in TIM_SlaveTimer_SetConfig()
7496 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7891 void TIM_ResetCallback(TIM_HandleTypeDef *htim) in TIM_ResetCallback() argument
7894 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; in TIM_ResetCallback()
7895 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; in TIM_ResetCallback()
7896 htim->TriggerCallback = HAL_TIM_TriggerCallback; in TIM_ResetCallback()
7897 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; in TIM_ResetCallback()
7898 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; in TIM_ResetCallback()
7899 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; in TIM_ResetCallback()
7900 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; in TIM_ResetCallback()
7901 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; in TIM_ResetCallback()
7902 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; in TIM_ResetCallback()
7903 htim->ErrorCallback = HAL_TIM_ErrorCallback; in TIM_ResetCallback()
7904 htim->CommutationCallback = HAL_TIMEx_CommutCallback; in TIM_ResetCallback()
7905 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; in TIM_ResetCallback()
7906 htim->BreakCallback = HAL_TIMEx_BreakCallback; in TIM_ResetCallback()
7907 htim->Break2Callback = HAL_TIMEx_Break2Callback; in TIM_ResetCallback()