Lines Matching refs:hdma
175 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32…
176 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
177 static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma);
178 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
179 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
216 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) in HAL_DMA_Init() argument
224 if(hdma == NULL) in HAL_DMA_Init()
230 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); in HAL_DMA_Init()
231 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); in HAL_DMA_Init()
232 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); in HAL_DMA_Init()
233 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); in HAL_DMA_Init()
234 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); in HAL_DMA_Init()
235 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); in HAL_DMA_Init()
236 assert_param(IS_DMA_MODE(hdma->Init.Mode)); in HAL_DMA_Init()
237 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); in HAL_DMA_Init()
239 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_Init()
241 assert_param(IS_DMA_REQUEST(hdma->Init.Request)); in HAL_DMA_Init()
242 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); in HAL_DMA_Init()
245 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) in HAL_DMA_Init()
247 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); in HAL_DMA_Init()
248 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); in HAL_DMA_Init()
249 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); in HAL_DMA_Init()
253 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Init()
256 __HAL_UNLOCK(hdma); in HAL_DMA_Init()
259 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Init()
262 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) in HAL_DMA_Init()
268 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_Init()
271 hdma->State = HAL_DMA_STATE_ERROR; in HAL_DMA_Init()
278 registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; in HAL_DMA_Init()
287 registerValue |= hdma->Init.Direction | in HAL_DMA_Init()
288 hdma->Init.PeriphInc | hdma->Init.MemInc | in HAL_DMA_Init()
289 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | in HAL_DMA_Init()
290 hdma->Init.Mode | hdma->Init.Priority; in HAL_DMA_Init()
293 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) in HAL_DMA_Init()
296 registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; in HAL_DMA_Init()
305 if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) in HAL_DMA_Init()
314 ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; in HAL_DMA_Init()
317 registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; in HAL_DMA_Init()
323 registerValue |= hdma->Init.FIFOMode; in HAL_DMA_Init()
326 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) in HAL_DMA_Init()
329 registerValue |= hdma->Init.FIFOThreshold; in HAL_DMA_Init()
333 if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) in HAL_DMA_Init()
335 if (DMA_CheckFifoParam(hdma) != HAL_OK) in HAL_DMA_Init()
338 hdma->ErrorCode = HAL_DMA_ERROR_PARAM; in HAL_DMA_Init()
341 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Init()
349 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; in HAL_DMA_Init()
353 regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_Init()
356 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_Init()
358 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ in HAL_DMA_Init()
360 if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) in HAL_DMA_Init()
363 assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); in HAL_DMA_Init()
367 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Init()
370 __HAL_UNLOCK(hdma); in HAL_DMA_Init()
373 registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; in HAL_DMA_Init()
382 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | in HAL_DMA_Init()
383 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | in HAL_DMA_Init()
384 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | in HAL_DMA_Init()
385 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | in HAL_DMA_Init()
386 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | in HAL_DMA_Init()
387 DMA_TO_BDMA_MODE(hdma->Init.Mode) | in HAL_DMA_Init()
388 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); in HAL_DMA_Init()
391 ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; in HAL_DMA_Init()
394 …hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_… in HAL_DMA_Init()
398 regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_Init()
401 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_Init()
405 hdma->ErrorCode = HAL_DMA_ERROR_PARAM; in HAL_DMA_Init()
406 hdma->State = HAL_DMA_STATE_ERROR; in HAL_DMA_Init()
411 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ in HAL_DMA_Init()
416 DMA_CalcDMAMUXChannelBaseAndMask(hdma); in HAL_DMA_Init()
418 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) in HAL_DMA_Init()
421 hdma->Init.Request = DMA_REQUEST_MEM2MEM; in HAL_DMA_Init()
425 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); in HAL_DMA_Init()
428 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_Init()
433 …if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7… in HAL_DMA_Init()
437 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); in HAL_DMA_Init()
440 hdma->DMAmuxRequestGen->RGCR = 0U; in HAL_DMA_Init()
443 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_Init()
447 hdma->DMAmuxRequestGen = 0U; in HAL_DMA_Init()
448 hdma->DMAmuxRequestGenStatus = 0U; in HAL_DMA_Init()
449 hdma->DMAmuxRequestGenStatusMask = 0U; in HAL_DMA_Init()
454 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Init()
457 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Init()
468 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) in HAL_DMA_DeInit() argument
474 if(hdma == NULL) in HAL_DMA_DeInit()
480 __HAL_DMA_DISABLE(hdma); in HAL_DMA_DeInit()
482 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_DeInit()
485 ((DMA_Stream_TypeDef *)hdma->Instance)->CR = 0U; in HAL_DMA_DeInit()
488 ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = 0U; in HAL_DMA_DeInit()
491 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = 0U; in HAL_DMA_DeInit()
494 ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = 0U; in HAL_DMA_DeInit()
497 ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = 0U; in HAL_DMA_DeInit()
500 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U; in HAL_DMA_DeInit()
503 regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_DeInit()
506 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_DeInit()
508 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ in HAL_DMA_DeInit()
511 ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = 0U; in HAL_DMA_DeInit()
514 ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U; in HAL_DMA_DeInit()
517 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = 0U; in HAL_DMA_DeInit()
520 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U; in HAL_DMA_DeInit()
523 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U; in HAL_DMA_DeInit()
526 regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_DeInit()
529 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_DeInit()
538 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ in HAL_DMA_DeInit()
543 DMA_CalcDMAMUXChannelBaseAndMask(hdma); in HAL_DMA_DeInit()
545 if(hdma->DMAmuxChannel != 0U) in HAL_DMA_DeInit()
548 hdma->DMAmuxChannel->CCR = 0U; in HAL_DMA_DeInit()
551 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_DeInit()
554 …if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7… in HAL_DMA_DeInit()
558 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); in HAL_DMA_DeInit()
561 hdma->DMAmuxRequestGen->RGCR = 0U; in HAL_DMA_DeInit()
564 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_DeInit()
567 hdma->DMAmuxRequestGen = 0U; in HAL_DMA_DeInit()
568 hdma->DMAmuxRequestGenStatus = 0U; in HAL_DMA_DeInit()
569 hdma->DMAmuxRequestGenStatusMask = 0U; in HAL_DMA_DeInit()
574 hdma->XferCpltCallback = NULL; in HAL_DMA_DeInit()
575 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_DeInit()
576 hdma->XferM1CpltCallback = NULL; in HAL_DMA_DeInit()
577 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_DeInit()
578 hdma->XferErrorCallback = NULL; in HAL_DMA_DeInit()
579 hdma->XferAbortCallback = NULL; in HAL_DMA_DeInit()
582 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_DeInit()
585 hdma->State = HAL_DMA_STATE_RESET; in HAL_DMA_DeInit()
588 __HAL_UNLOCK(hdma); in HAL_DMA_DeInit()
625 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, … in HAL_DMA_Start() argument
633 if(hdma == NULL) in HAL_DMA_Start()
639 __HAL_LOCK(hdma); in HAL_DMA_Start()
641 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_Start()
644 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start()
647 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start()
650 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Start()
653 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start()
656 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start()
661 hdma->ErrorCode = HAL_DMA_ERROR_BUSY; in HAL_DMA_Start()
664 __HAL_UNLOCK(hdma); in HAL_DMA_Start()
681 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres… in HAL_DMA_Start_IT() argument
689 if(hdma == NULL) in HAL_DMA_Start_IT()
695 __HAL_LOCK(hdma); in HAL_DMA_Start_IT()
697 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_Start_IT()
700 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start_IT()
703 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start_IT()
706 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Start_IT()
709 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start_IT()
711 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_Start_IT()
714 …MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA… in HAL_DMA_Start_IT()
716 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_Start_IT()
719 ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; in HAL_DMA_Start_IT()
725 …MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_… in HAL_DMA_Start_IT()
727 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_Start_IT()
730 ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; in HAL_DMA_Start_IT()
734 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ in HAL_DMA_Start_IT()
737 if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) in HAL_DMA_Start_IT()
740 hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; in HAL_DMA_Start_IT()
743 if(hdma->DMAmuxRequestGen != 0U) in HAL_DMA_Start_IT()
747 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; in HAL_DMA_Start_IT()
752 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start_IT()
757 hdma->ErrorCode = HAL_DMA_ERROR_BUSY; in HAL_DMA_Start_IT()
760 __HAL_UNLOCK(hdma); in HAL_DMA_Start_IT()
781 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort() argument
791 if(hdma == NULL) in HAL_DMA_Abort()
797 if(hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort()
799 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort()
802 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
809 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_Abort()
812 …((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); in HAL_DMA_Abort()
813 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); in HAL_DMA_Abort()
815 enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); in HAL_DMA_Abort()
820 …((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEI… in HAL_DMA_Abort()
822 enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); in HAL_DMA_Abort()
825 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ in HAL_DMA_Abort()
828 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMA_Abort()
832 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort()
841 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_Abort()
844 hdma->State = HAL_DMA_STATE_ERROR; in HAL_DMA_Abort()
847 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
854 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_Abort()
856 regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_Abort()
857 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_Abort()
861 regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_Abort()
862 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_Abort()
865 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ in HAL_DMA_Abort()
868 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_Abort()
870 if(hdma->DMAmuxRequestGen != 0U) in HAL_DMA_Abort()
874 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; in HAL_DMA_Abort()
877 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_Abort()
882 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Abort()
885 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
897 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort_IT() argument
902 if(hdma == NULL) in HAL_DMA_Abort_IT()
907 if(hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort_IT()
909 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort_IT()
914 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_Abort_IT()
917 hdma->State = HAL_DMA_STATE_ABORT; in HAL_DMA_Abort_IT()
920 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort_IT()
925 …((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEI… in HAL_DMA_Abort_IT()
928 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort_IT()
930 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ in HAL_DMA_Abort_IT()
933 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMA_Abort_IT()
936 regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_Abort_IT()
937 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_Abort_IT()
940 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_Abort_IT()
942 if(hdma->DMAmuxRequestGen != 0U) in HAL_DMA_Abort_IT()
946 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; in HAL_DMA_Abort_IT()
949 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_Abort_IT()
954 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Abort_IT()
957 __HAL_UNLOCK(hdma); in HAL_DMA_Abort_IT()
960 if(hdma->XferAbortCallback != NULL) in HAL_DMA_Abort_IT()
962 hdma->XferAbortCallback(hdma); in HAL_DMA_Abort_IT()
981 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com… in HAL_DMA_PollForTransfer() argument
993 if(hdma == NULL) in HAL_DMA_PollForTransfer()
998 if(HAL_DMA_STATE_BUSY != hdma->State) in HAL_DMA_PollForTransfer()
1001 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_PollForTransfer()
1002 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
1007 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_PollForTransfer()
1010 if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U) in HAL_DMA_PollForTransfer()
1012 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; in HAL_DMA_PollForTransfer()
1020 cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
1025 cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
1028 isr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); in HAL_DMA_PollForTransfer()
1029 ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); in HAL_DMA_PollForTransfer()
1034 if ((((BDMA_Channel_TypeDef *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U) in HAL_DMA_PollForTransfer()
1036 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; in HAL_DMA_PollForTransfer()
1044 cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
1049 cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
1052 isr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); in HAL_DMA_PollForTransfer()
1053 ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); in HAL_DMA_PollForTransfer()
1058 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_PollForTransfer()
1060 if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_PollForTransfer()
1063 hdma->ErrorCode |= HAL_DMA_ERROR_FE; in HAL_DMA_PollForTransfer()
1066 (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
1069 if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_PollForTransfer()
1072 hdma->ErrorCode |= HAL_DMA_ERROR_DME; in HAL_DMA_PollForTransfer()
1075 (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
1078 if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_PollForTransfer()
1081 hdma->ErrorCode |= HAL_DMA_ERROR_TE; in HAL_DMA_PollForTransfer()
1084 (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
1087 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
1090 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
1097 if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_PollForTransfer()
1102 (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_PollForTransfer()
1105 hdma->ErrorCode = HAL_DMA_ERROR_TE; in HAL_DMA_PollForTransfer()
1108 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
1111 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
1123 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_PollForTransfer()
1127 (void) HAL_DMA_Abort(hdma); in HAL_DMA_PollForTransfer()
1139 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ in HAL_DMA_PollForTransfer()
1142 if(hdma->DMAmuxRequestGen != 0U) in HAL_DMA_PollForTransfer()
1145 if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) in HAL_DMA_PollForTransfer()
1148 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_PollForTransfer()
1151 hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; in HAL_DMA_PollForTransfer()
1156 if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) in HAL_DMA_PollForTransfer()
1159 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_PollForTransfer()
1162 hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; in HAL_DMA_PollForTransfer()
1172 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_PollForTransfer()
1174 (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
1178 (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_PollForTransfer()
1181 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
1184 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
1189 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_PollForTransfer()
1191 (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU); in HAL_DMA_PollForTransfer()
1195 (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_PollForTransfer()
1208 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) in HAL_DMA_IRQHandler() argument
1216 DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_IRQHandler()
1217 BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_IRQHandler()
1222 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in HAL_DMA_IRQHandler()
1225 if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_IRQHandler()
1227 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) in HAL_DMA_IRQHandler()
1230 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); in HAL_DMA_IRQHandler()
1233 regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1236 hdma->ErrorCode |= HAL_DMA_ERROR_TE; in HAL_DMA_IRQHandler()
1240 if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_IRQHandler()
1242 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) in HAL_DMA_IRQHandler()
1245 regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1248 hdma->ErrorCode |= HAL_DMA_ERROR_FE; in HAL_DMA_IRQHandler()
1252 if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_IRQHandler()
1254 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) in HAL_DMA_IRQHandler()
1257 regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1260 hdma->ErrorCode |= HAL_DMA_ERROR_DME; in HAL_DMA_IRQHandler()
1264 if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_IRQHandler()
1266 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) in HAL_DMA_IRQHandler()
1269 regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1272 if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) in HAL_DMA_IRQHandler()
1275 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) in HAL_DMA_IRQHandler()
1277 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
1280 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
1286 if(hdma->XferM1HalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
1289 hdma->XferM1HalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
1296 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) in HAL_DMA_IRQHandler()
1299 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); in HAL_DMA_IRQHandler()
1302 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
1305 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
1311 if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) in HAL_DMA_IRQHandler()
1313 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) in HAL_DMA_IRQHandler()
1316 regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1318 if(HAL_DMA_STATE_ABORT == hdma->State) in HAL_DMA_IRQHandler()
1321 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); in HAL_DMA_IRQHandler()
1322 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); in HAL_DMA_IRQHandler()
1324 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) in HAL_DMA_IRQHandler()
1326 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); in HAL_DMA_IRQHandler()
1330 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1333 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
1336 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
1338 if(hdma->XferAbortCallback != NULL) in HAL_DMA_IRQHandler()
1340 hdma->XferAbortCallback(hdma); in HAL_DMA_IRQHandler()
1345 if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) in HAL_DMA_IRQHandler()
1348 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) in HAL_DMA_IRQHandler()
1350 if(hdma->XferM1CpltCallback != NULL) in HAL_DMA_IRQHandler()
1353 hdma->XferM1CpltCallback(hdma); in HAL_DMA_IRQHandler()
1359 if(hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
1362 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
1369 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) in HAL_DMA_IRQHandler()
1372 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); in HAL_DMA_IRQHandler()
1375 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
1378 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
1381 if(hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
1384 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
1391 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) in HAL_DMA_IRQHandler()
1393 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) in HAL_DMA_IRQHandler()
1395 hdma->State = HAL_DMA_STATE_ABORT; in HAL_DMA_IRQHandler()
1398 __HAL_DMA_DISABLE(hdma); in HAL_DMA_IRQHandler()
1407 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); in HAL_DMA_IRQHandler()
1409 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) in HAL_DMA_IRQHandler()
1412 hdma->State = HAL_DMA_STATE_ERROR; in HAL_DMA_IRQHandler()
1417 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
1421 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
1424 if(hdma->XferErrorCallback != NULL) in HAL_DMA_IRQHandler()
1427 hdma->XferErrorCallback(hdma); in HAL_DMA_IRQHandler()
1431 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ in HAL_DMA_IRQHandler()
1433 ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); in HAL_DMA_IRQHandler()
1436 …if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR… in HAL_DMA_IRQHandler()
1439 regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_IRQHandler()
1447 if(hdma->XferM1HalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
1450 hdma->XferM1HalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
1456 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
1459 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
1468 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); in HAL_DMA_IRQHandler()
1474 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
1477 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
1483 …else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDM… in HAL_DMA_IRQHandler()
1486 regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1494 if(hdma->XferM1CpltCallback != NULL) in HAL_DMA_IRQHandler()
1497 hdma->XferM1CpltCallback(hdma); in HAL_DMA_IRQHandler()
1503 if(hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
1506 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
1515 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); in HAL_DMA_IRQHandler()
1518 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
1521 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
1524 if(hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
1527 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
1532 …else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDM… in HAL_DMA_IRQHandler()
1537 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); in HAL_DMA_IRQHandler()
1540 regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1543 hdma->ErrorCode = HAL_DMA_ERROR_TE; in HAL_DMA_IRQHandler()
1546 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
1549 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
1551 if (hdma->XferErrorCallback != NULL) in HAL_DMA_IRQHandler()
1554 hdma->XferErrorCallback(hdma); in HAL_DMA_IRQHandler()
1578 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb… in HAL_DMA_RegisterCallback() argument
1584 if(hdma == NULL) in HAL_DMA_RegisterCallback()
1590 __HAL_LOCK(hdma); in HAL_DMA_RegisterCallback()
1592 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_RegisterCallback()
1597 hdma->XferCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
1601 hdma->XferHalfCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
1605 hdma->XferM1CpltCallback = pCallback; in HAL_DMA_RegisterCallback()
1609 hdma->XferM1HalfCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
1613 hdma->XferErrorCallback = pCallback; in HAL_DMA_RegisterCallback()
1617 hdma->XferAbortCallback = pCallback; in HAL_DMA_RegisterCallback()
1632 __HAL_UNLOCK(hdma); in HAL_DMA_RegisterCallback()
1645 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal… in HAL_DMA_UnRegisterCallback() argument
1650 if(hdma == NULL) in HAL_DMA_UnRegisterCallback()
1656 __HAL_LOCK(hdma); in HAL_DMA_UnRegisterCallback()
1658 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_UnRegisterCallback()
1663 hdma->XferCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1667 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1671 hdma->XferM1CpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1675 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1679 hdma->XferErrorCallback = NULL; in HAL_DMA_UnRegisterCallback()
1683 hdma->XferAbortCallback = NULL; in HAL_DMA_UnRegisterCallback()
1687 hdma->XferCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1688 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1689 hdma->XferM1CpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1690 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1691 hdma->XferErrorCallback = NULL; in HAL_DMA_UnRegisterCallback()
1692 hdma->XferAbortCallback = NULL; in HAL_DMA_UnRegisterCallback()
1706 __HAL_UNLOCK(hdma); in HAL_DMA_UnRegisterCallback()
1736 HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma) in HAL_DMA_GetState() argument
1738 return hdma->State; in HAL_DMA_GetState()
1747 uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma) in HAL_DMA_GetError() argument
1749 return hdma->ErrorCode; in HAL_DMA_GetError()
1773 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32… in DMA_SetConfig() argument
1776 DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; in DMA_SetConfig()
1777 BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; in DMA_SetConfig()
1779 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ in DMA_SetConfig()
1782 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in DMA_SetConfig()
1784 if(hdma->DMAmuxRequestGen != 0U) in DMA_SetConfig()
1787 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in DMA_SetConfig()
1791 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in DMA_SetConfig()
1794 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in DMA_SetConfig()
1797 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); in DMA_SetConfig()
1800 ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; in DMA_SetConfig()
1803 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) in DMA_SetConfig()
1806 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; in DMA_SetConfig()
1809 ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; in DMA_SetConfig()
1815 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; in DMA_SetConfig()
1818 ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; in DMA_SetConfig()
1821 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ in DMA_SetConfig()
1824 regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); in DMA_SetConfig()
1827 ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; in DMA_SetConfig()
1830 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) in DMA_SetConfig()
1833 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; in DMA_SetConfig()
1836 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; in DMA_SetConfig()
1842 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; in DMA_SetConfig()
1845 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; in DMA_SetConfig()
1860 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) in DMA_CalcBaseAndBitshift() argument
1862 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ in DMA_CalcBaseAndBitshift()
1864 uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; in DMA_CalcBaseAndBitshift()
1868 hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; in DMA_CalcBaseAndBitshift()
1873 … hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); in DMA_CalcBaseAndBitshift()
1878 hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); in DMA_CalcBaseAndBitshift()
1884 hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); in DMA_CalcBaseAndBitshift()
1887 return hdma->StreamBaseAddress; in DMA_CalcBaseAndBitshift()
1896 static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma) in DMA_CheckFifoParam() argument
1901 if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) in DMA_CheckFifoParam()
1903 switch (hdma->Init.FIFOThreshold) in DMA_CheckFifoParam()
1908 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1915 if (hdma->Init.MemBurst == DMA_MBURST_INC16) in DMA_CheckFifoParam()
1930 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) in DMA_CheckFifoParam()
1932 switch (hdma->Init.FIFOThreshold) in DMA_CheckFifoParam()
1940 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1947 if (hdma->Init.MemBurst == DMA_MBURST_INC16) in DMA_CheckFifoParam()
1961 switch (hdma->Init.FIFOThreshold) in DMA_CheckFifoParam()
1970 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1990 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) in DMA_CalcDMAMUXChannelBaseAndMask() argument
1993 uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); in DMA_CalcDMAMUXChannelBaseAndMask()
1995 if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) in DMA_CalcDMAMUXChannelBaseAndMask()
1998 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; in DMA_CalcDMAMUXChannelBaseAndMask()
1999 …hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream… in DMA_CalcDMAMUXChannelBaseAndMask()
2000 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; in DMA_CalcDMAMUXChannelBaseAndMask()
2001 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); in DMA_CalcDMAMUXChannelBaseAndMask()
2006 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; in DMA_CalcDMAMUXChannelBaseAndMask()
2013 …hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream… in DMA_CalcDMAMUXChannelBaseAndMask()
2014 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; in DMA_CalcDMAMUXChannelBaseAndMask()
2015 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); in DMA_CalcDMAMUXChannelBaseAndMask()
2025 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) in DMA_CalcDMAMUXRequestGenBaseAndMask() argument
2027 uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; in DMA_CalcDMAMUXRequestGenBaseAndMask()
2031 if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) in DMA_CalcDMAMUXRequestGenBaseAndMask()
2034 …hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenera… in DMA_CalcDMAMUXRequestGenBaseAndMask()
2036 hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; in DMA_CalcDMAMUXRequestGenBaseAndMask()
2041 …hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenera… in DMA_CalcDMAMUXRequestGenBaseAndMask()
2043 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; in DMA_CalcDMAMUXRequestGenBaseAndMask()
2046 hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); in DMA_CalcDMAMUXRequestGenBaseAndMask()