Lines Matching refs:IFCR

116   __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */  member
122 __IO uint32_t IFCR; /*!< BDMA interrupt flag clear register */ member
356 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_Init()
401 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_Init()
506 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_DeInit()
529 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_DeInit()
857 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_Abort()
862 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_Abort()
937 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_Abort_IT()
1029 ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); in HAL_DMA_PollForTransfer()
1053 ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); in HAL_DMA_PollForTransfer()
1233 regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1245 regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1257 regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1269 regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1316 regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1330 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1439 regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); in HAL_DMA_IRQHandler()
1486 regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1540 regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); in HAL_DMA_IRQHandler()
1794 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); in DMA_SetConfig()
1824 regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); in DMA_SetConfig()