Lines Matching refs:PWR
34 #if defined (PWR)
329 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
336 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
363 MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode); in LL_PWR_SetRegulModeDS()
375 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS)); in LL_PWR_GetRegulModeDS()
385 SET_BIT(PWR->CR1, PWR_CR1_PVDEN); in LL_PWR_EnablePVD()
395 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN); in LL_PWR_DisablePVD()
405 return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
424 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); in LL_PWR_SetPVDLevel()
442 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS)); in LL_PWR_GetPVDLevel()
452 SET_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_EnableBkUpAccess()
462 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_DisableBkUpAccess()
472 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpAccess()
482 SET_BIT(PWR->CR1, PWR_CR1_FLPS); in LL_PWR_EnableFlashPowerDown()
492 CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS); in LL_PWR_DisableFlashPowerDown()
502 return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL); in LL_PWR_IsEnabledFlashPowerDown()
513 SET_BIT(PWR->CR1, PWR_CR1_BOOSTE); in LL_PWR_EnableAnalogBooster()
523 CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE); in LL_PWR_DisableAnalogBooster()
533 return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL); in LL_PWR_IsEnabledAnalogBooster()
545 SET_BIT(PWR->CR1, PWR_CR1_AVD_READY); in LL_PWR_EnableAnalogVoltageReady()
555 CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY); in LL_PWR_DisableAnalogVoltageReady()
565 return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL); in LL_PWR_IsEnabledAnalogVoltageReady()
580 MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling); in LL_PWR_SetStopModeRegulVoltageScaling()
593 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS)); in LL_PWR_GetStopModeRegulVoltageScaling()
603 SET_BIT(PWR->CR1, PWR_CR1_AVDEN); in LL_PWR_EnableAVD()
613 CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN); in LL_PWR_DisableAVD()
623 return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledAVD()
638 MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel); in LL_PWR_SetAVDLevel()
652 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS)); in LL_PWR_GetAVDLevel()
663 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); in LL_PWR_EnableAXIRAM1ShutOff()
673 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); in LL_PWR_DisableAXIRAM1ShutOff()
683 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAXIRAM1ShutOff()
695 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); in LL_PWR_EnableAXIRAM2ShutOff()
705 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); in LL_PWR_DisableAXIRAM2ShutOff()
715 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAXIRAM2ShutOff()
727 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); in LL_PWR_EnableAXIRAM3ShutOff()
737 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); in LL_PWR_DisableAXIRAM3ShutOff()
747 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAXIRAM3ShutOff()
759 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); in LL_PWR_EnableAHBRAM1ShutOff()
769 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); in LL_PWR_DisableAHBRAM1ShutOff()
779 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAHBRAM1ShutOff()
791 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); in LL_PWR_EnableAHBRAM2ShutOff()
801 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); in LL_PWR_DisableAHBRAM2ShutOff()
811 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAHBRAM2ShutOff()
823 SET_BIT(PWR->CR1, PWR_CR1_ITCMSO); in LL_PWR_EnableITCMSOShutOff()
833 CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO); in LL_PWR_DisableITCMSOShutOff()
843 return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL); in LL_PWR_IsEnabledITCMShutOff()
855 SET_BIT(PWR->CR1, PWR_CR1_HSITFSO); in LL_PWR_EnableHSITFShutOff()
865 CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO); in LL_PWR_DisableHSITFShutOff()
875 return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL); in LL_PWR_IsEnabledHSITFShutOff()
887 SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); in LL_PWR_EnableSRDRAMShutOff()
897 CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); in LL_PWR_DisableSRDRAMShutOff()
907 return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL); in LL_PWR_IsEnabledSRDRAMShutOff()
923 SET_BIT(PWR->CR2, PWR_CR2_BREN); in LL_PWR_EnableBkUpRegulator()
933 CLEAR_BIT(PWR->CR2, PWR_CR2_BREN); in LL_PWR_DisableBkUpRegulator()
943 return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpRegulator()
953 SET_BIT(PWR->CR2, PWR_CR2_MONEN); in LL_PWR_EnableMonitoring()
963 CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN); in LL_PWR_DisableMonitoring()
973 return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledMonitoring()
999 …MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR… in LL_PWR_ConfigSupply()
1015 MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource); in LL_PWR_ConfigSupply()
1041 …return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_… in LL_PWR_GetSupply()
1056 return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS))); in LL_PWR_GetSupply()
1067 SET_BIT(PWR->CR3, PWR_CR3_VBE); in LL_PWR_EnableBatteryCharging()
1077 CLEAR_BIT(PWR->CR3, PWR_CR3_VBE); in LL_PWR_DisableBatteryCharging()
1087 return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL); in LL_PWR_IsEnabledBatteryCharging()
1100 MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
1112 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS)); in LL_PWR_GetBattChargResistor()
1122 SET_BIT(PWR->CR3, PWR_CR3_USBREGEN); in LL_PWR_EnableUSBReg()
1132 CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN); in LL_PWR_DisableUSBReg()
1142 return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledUSBReg()
1152 SET_BIT(PWR->CR3, PWR_CR3_USB33DEN); in LL_PWR_EnableUSBVoltageDetector()
1162 CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN); in LL_PWR_DisableUSBVoltageDetector()
1172 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledUSBVoltageDetector()
1186 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode); in LL_PWR_CPU_SetD1PowerMode()
1199 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode); in LL_PWR_CPU_SetCDPowerMode()
1214 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode); in LL_PWR_CPU2_SetD1PowerMode()
1228 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1)); in LL_PWR_CPU_GetD1PowerMode()
1240 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD)); in LL_PWR_CPU_GetCDPowerMode()
1254 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1)); in LL_PWR_CPU2_GetD1PowerMode()
1269 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode); in LL_PWR_CPU_SetD2PowerMode()
1284 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode); in LL_PWR_CPU2_SetD2PowerMode()
1298 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2)); in LL_PWR_CPU_GetD2PowerMode()
1312 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2)); in LL_PWR_CPU2_GetD2PowerMode()
1327 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode); in LL_PWR_CPU_SetD3PowerMode()
1340 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode); in LL_PWR_CPU_SetSRDPowerMode()
1355 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode); in LL_PWR_CPU2_SetD3PowerMode()
1369 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3)); in LL_PWR_CPU_GetD3PowerMode()
1381 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD)); in LL_PWR_CPU_GetSRDPowerMode()
1395 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3)); in LL_PWR_CPU2_GetD3PowerMode()
1407 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); in LL_PWR_HoldCPU1()
1417 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); in LL_PWR_ReleaseCPU1()
1427 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1)) ? 1UL : 0UL); in LL_PWR_IsCPU1Held()
1437 SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); in LL_PWR_HoldCPU2()
1447 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); in LL_PWR_ReleaseCPU2()
1457 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL); in LL_PWR_IsCPU2Held()
1469 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); in LL_PWR_CPU_EnableD3RunInLowPowerMode()
1479 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); in LL_PWR_CPU_EnableSRDRunInLowPowerMode()
1491 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); in LL_PWR_CPU2_EnableD3RunInLowPowerMode()
1503 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); in LL_PWR_CPU_DisableD3RunInLowPowerMode()
1513 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); in LL_PWR_CPU_DisableSRDRunInLowPowerMode()
1525 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); in LL_PWR_CPU2_DisableD3RunInLowPowerMode()
1537 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL); in LL_PWR_CPU_IsEnabledD3RunInLowPowerMode()
1547 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL); in LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode()
1559 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL); in LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode()
1578 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
1580 MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
1598 return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS)); in LL_PWR_GetRegulVoltageScaling()
1600 return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS)); in LL_PWR_GetRegulVoltageScaling()
1626 SET_BIT(PWR->WKUPEPR, WakeUpPin); in LL_PWR_EnableWakeUpPin()
1651 CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); in LL_PWR_DisableWakeUpPin()
1676 return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
1701 SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); in LL_PWR_SetWakeUpPinPolarityLow()
1726 CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); in LL_PWR_SetWakeUpPinPolarityHigh()
1751 …return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEP… in LL_PWR_IsWakeUpPinPolarityLow()
1776 MODIFY_REG(PWR->WKUPEPR, \ in LL_PWR_SetWakeUpPinPullNone()
1803 MODIFY_REG(PWR->WKUPEPR, \ in LL_PWR_SetWakeUpPinPullUp()
1830 MODIFY_REG(PWR->WKUPEPR, \ in LL_PWR_SetWakeUpPinPullDown()
1860 …uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHI… in LL_PWR_GetWakeUpPinPull()
1880 return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
1890 return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_ACTVOS()
1900 return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_AVDO()
1911 return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_MMCVDO()
1922 return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_BRR()
1932 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATL()
1942 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATH()
1952 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPL()
1962 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPH()
1973 return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SMPSEXT()
1984 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_USB()
1995 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_HOLD2()
2005 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_HOLD1()
2016 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL); in LL_PWR_CPU_IsActiveFlag_STOP()
2027 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL); in LL_PWR_CPU2_IsActiveFlag_STOP()
2038 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL); in LL_PWR_CPU_IsActiveFlag_SB()
2049 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL); in LL_PWR_CPU2_IsActiveFlag_SB()
2061 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL); in LL_PWR_CPU_IsActiveFlag_SB_D1()
2073 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL); in LL_PWR_CPU2_IsActiveFlag_SB_D1()
2085 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL); in LL_PWR_CPU_IsActiveFlag_SB_D2()
2097 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL); in LL_PWR_CPU2_IsActiveFlag_SB_D2()
2111 return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
2113 return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
2124 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU6()
2135 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU5()
2146 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU4()
2157 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
2168 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
2178 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
2188 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); in LL_PWR_ClearFlag_CPU()
2199 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); in LL_PWR_ClearFlag_CPU2()
2210 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6); in LL_PWR_ClearFlag_WU6()
2221 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5); in LL_PWR_ClearFlag_WU5()
2232 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4); in LL_PWR_ClearFlag_WU4()
2243 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3); in LL_PWR_ClearFlag_WU3()
2254 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2); in LL_PWR_ClearFlag_WU2()
2264 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1); in LL_PWR_ClearFlag_WU1()