Lines Matching refs:Periphs
566 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) in LL_AHB3_GRP1_EnableClock() argument
569 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
571 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
616 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB3_GRP1_IsEnabledClock() argument
618 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB3_GRP1_IsEnabledClock()
662 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) in LL_AHB3_GRP1_DisableClock() argument
664 CLEAR_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_DisableClock()
698 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) in LL_AHB3_GRP1_ForceReset() argument
700 SET_BIT(RCC->AHB3RSTR, Periphs); in LL_AHB3_GRP1_ForceReset()
734 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB3_GRP1_ReleaseReset() argument
736 CLEAR_BIT(RCC->AHB3RSTR, Periphs); in LL_AHB3_GRP1_ReleaseReset()
779 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) in LL_AHB3_GRP1_EnableClockSleep() argument
782 SET_BIT(RCC->AHB3LPENR, Periphs); in LL_AHB3_GRP1_EnableClockSleep()
784 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); in LL_AHB3_GRP1_EnableClockSleep()
828 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) in LL_AHB3_GRP1_DisableClockSleep() argument
830 CLEAR_BIT(RCC->AHB3LPENR, Periphs); in LL_AHB3_GRP1_DisableClockSleep()
872 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_AHB1_GRP1_EnableClock() argument
875 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
877 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
912 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB1_GRP1_IsEnabledClock() argument
914 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB1_GRP1_IsEnabledClock()
948 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_AHB1_GRP1_DisableClock() argument
950 CLEAR_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_DisableClock()
976 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) in LL_AHB1_GRP1_ForceReset() argument
978 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
1004 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB1_GRP1_ReleaseReset() argument
1006 CLEAR_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ReleaseReset()
1040 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) in LL_AHB1_GRP1_EnableClockSleep() argument
1043 SET_BIT(RCC->AHB1LPENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep()
1045 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep()
1080 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) in LL_AHB1_GRP1_DisableClockSleep() argument
1082 CLEAR_BIT(RCC->AHB1LPENR, Periphs); in LL_AHB1_GRP1_DisableClockSleep()
1124 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) in LL_AHB2_GRP1_EnableClock() argument
1127 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
1129 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
1164 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB2_GRP1_IsEnabledClock() argument
1166 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB2_GRP1_IsEnabledClock()
1200 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) in LL_AHB2_GRP1_DisableClock() argument
1202 CLEAR_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_DisableClock()
1230 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) in LL_AHB2_GRP1_ForceReset() argument
1232 SET_BIT(RCC->AHB2RSTR, Periphs); in LL_AHB2_GRP1_ForceReset()
1260 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB2_GRP1_ReleaseReset() argument
1262 CLEAR_BIT(RCC->AHB2RSTR, Periphs); in LL_AHB2_GRP1_ReleaseReset()
1294 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) in LL_AHB2_GRP1_EnableClockSleep() argument
1297 SET_BIT(RCC->AHB2LPENR, Periphs); in LL_AHB2_GRP1_EnableClockSleep()
1299 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); in LL_AHB2_GRP1_EnableClockSleep()
1330 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) in LL_AHB2_GRP1_DisableClockSleep() argument
1332 CLEAR_BIT(RCC->AHB2LPENR, Periphs); in LL_AHB2_GRP1_DisableClockSleep()
1384 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) in LL_AHB4_GRP1_EnableClock() argument
1387 SET_BIT(RCC->AHB4ENR, Periphs); in LL_AHB4_GRP1_EnableClock()
1389 tmpreg = READ_BIT(RCC->AHB4ENR, Periphs); in LL_AHB4_GRP1_EnableClock()
1434 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) in LL_AHB4_GRP1_IsEnabledClock() argument
1436 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); in LL_AHB4_GRP1_IsEnabledClock()
1480 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) in LL_AHB4_GRP1_DisableClock() argument
1482 CLEAR_BIT(RCC->AHB4ENR, Periphs); in LL_AHB4_GRP1_DisableClock()
1522 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) in LL_AHB4_GRP1_ForceReset() argument
1524 SET_BIT(RCC->AHB4RSTR, Periphs); in LL_AHB4_GRP1_ForceReset()
1564 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) in LL_AHB4_GRP1_ReleaseReset() argument
1566 CLEAR_BIT(RCC->AHB4RSTR, Periphs); in LL_AHB4_GRP1_ReleaseReset()
1606 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) in LL_AHB4_GRP1_EnableClockSleep() argument
1609 SET_BIT(RCC->AHB4LPENR, Periphs); in LL_AHB4_GRP1_EnableClockSleep()
1611 tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs); in LL_AHB4_GRP1_EnableClockSleep()
1652 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) in LL_AHB4_GRP1_DisableClockSleep() argument
1654 CLEAR_BIT(RCC->AHB4LPENR, Periphs); in LL_AHB4_GRP1_DisableClockSleep()
1678 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) in LL_APB3_GRP1_EnableClock() argument
1681 SET_BIT(RCC->APB3ENR, Periphs); in LL_APB3_GRP1_EnableClock()
1683 tmpreg = READ_BIT(RCC->APB3ENR, Periphs); in LL_APB3_GRP1_EnableClock()
1700 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) in LL_APB3_GRP1_IsEnabledClock() argument
1702 return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1U : 0U); in LL_APB3_GRP1_IsEnabledClock()
1718 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) in LL_APB3_GRP1_DisableClock() argument
1720 CLEAR_BIT(RCC->APB3ENR, Periphs); in LL_APB3_GRP1_DisableClock()
1734 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) in LL_APB3_GRP1_ForceReset() argument
1736 SET_BIT(RCC->APB3RSTR, Periphs); in LL_APB3_GRP1_ForceReset()
1750 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) in LL_APB3_GRP1_ReleaseReset() argument
1752 CLEAR_BIT(RCC->APB3RSTR, Periphs); in LL_APB3_GRP1_ReleaseReset()
1768 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs) in LL_APB3_GRP1_EnableClockSleep() argument
1771 SET_BIT(RCC->APB3LPENR, Periphs); in LL_APB3_GRP1_EnableClockSleep()
1773 tmpreg = READ_BIT(RCC->APB3LPENR, Periphs); in LL_APB3_GRP1_EnableClockSleep()
1790 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs) in LL_APB3_GRP1_DisableClockSleep() argument
1792 CLEAR_BIT(RCC->APB3LPENR, Periphs); in LL_APB3_GRP1_DisableClockSleep()
1862 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) in LL_APB1_GRP1_EnableClock() argument
1865 SET_BIT(RCC->APB1LENR, Periphs); in LL_APB1_GRP1_EnableClock()
1867 tmpreg = READ_BIT(RCC->APB1LENR, Periphs); in LL_APB1_GRP1_EnableClock()
1930 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_APB1_GRP1_IsEnabledClock() argument
1932 return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs) ? 1U : 0U); in LL_APB1_GRP1_IsEnabledClock()
1994 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) in LL_APB1_GRP1_DisableClock() argument
1996 CLEAR_BIT(RCC->APB1LENR, Periphs); in LL_APB1_GRP1_DisableClock()
2056 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) in LL_APB1_GRP1_ForceReset() argument
2058 SET_BIT(RCC->APB1LRSTR, Periphs); in LL_APB1_GRP1_ForceReset()
2118 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) in LL_APB1_GRP1_ReleaseReset() argument
2120 CLEAR_BIT(RCC->APB1LRSTR, Periphs); in LL_APB1_GRP1_ReleaseReset()
2182 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) in LL_APB1_GRP1_EnableClockSleep() argument
2185 SET_BIT(RCC->APB1LLPENR, Periphs); in LL_APB1_GRP1_EnableClockSleep()
2187 tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs); in LL_APB1_GRP1_EnableClockSleep()
2250 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) in LL_APB1_GRP1_DisableClockSleep() argument
2252 CLEAR_BIT(RCC->APB1LLPENR, Periphs); in LL_APB1_GRP1_DisableClockSleep()
2274 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) in LL_APB1_GRP2_EnableClock() argument
2277 SET_BIT(RCC->APB1HENR, Periphs); in LL_APB1_GRP2_EnableClock()
2279 tmpreg = READ_BIT(RCC->APB1HENR, Periphs); in LL_APB1_GRP2_EnableClock()
2302 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) in LL_APB1_GRP2_IsEnabledClock() argument
2304 return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs) ? 1U : 0U); in LL_APB1_GRP2_IsEnabledClock()
2326 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) in LL_APB1_GRP2_DisableClock() argument
2328 CLEAR_BIT(RCC->APB1HENR, Periphs); in LL_APB1_GRP2_DisableClock()
2350 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) in LL_APB1_GRP2_ForceReset() argument
2352 SET_BIT(RCC->APB1HRSTR, Periphs); in LL_APB1_GRP2_ForceReset()
2374 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) in LL_APB1_GRP2_ReleaseReset() argument
2376 CLEAR_BIT(RCC->APB1HRSTR, Periphs); in LL_APB1_GRP2_ReleaseReset()
2398 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs) in LL_APB1_GRP2_EnableClockSleep() argument
2401 SET_BIT(RCC->APB1HLPENR, Periphs); in LL_APB1_GRP2_EnableClockSleep()
2403 tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs); in LL_APB1_GRP2_EnableClockSleep()
2426 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) in LL_APB1_GRP2_DisableClockSleep() argument
2428 CLEAR_BIT(RCC->APB1HLPENR, Periphs); in LL_APB1_GRP2_DisableClockSleep()
2480 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) in LL_APB2_GRP1_EnableClock() argument
2483 SET_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_EnableClock()
2485 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_EnableClock()
2530 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) in LL_APB2_GRP1_IsEnabledClock() argument
2532 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1U : 0U); in LL_APB2_GRP1_IsEnabledClock()
2576 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) in LL_APB2_GRP1_DisableClock() argument
2578 CLEAR_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_DisableClock()
2622 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) in LL_APB2_GRP1_ForceReset() argument
2624 SET_BIT(RCC->APB2RSTR, Periphs); in LL_APB2_GRP1_ForceReset()
2668 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) in LL_APB2_GRP1_ReleaseReset() argument
2670 CLEAR_BIT(RCC->APB2RSTR, Periphs); in LL_APB2_GRP1_ReleaseReset()
2714 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) in LL_APB2_GRP1_EnableClockSleep() argument
2717 SET_BIT(RCC->APB2LPENR, Periphs); in LL_APB2_GRP1_EnableClockSleep()
2719 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); in LL_APB2_GRP1_EnableClockSleep()
2764 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) in LL_APB2_GRP1_DisableClockSleep() argument
2766 CLEAR_BIT(RCC->APB2LPENR, Periphs); in LL_APB2_GRP1_DisableClockSleep()
2814 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs) in LL_APB4_GRP1_EnableClock() argument
2817 SET_BIT(RCC->APB4ENR, Periphs); in LL_APB4_GRP1_EnableClock()
2819 tmpreg = READ_BIT(RCC->APB4ENR, Periphs); in LL_APB4_GRP1_EnableClock()
2860 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs) in LL_APB4_GRP1_IsEnabledClock() argument
2862 return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs) ? 1U : 0U); in LL_APB4_GRP1_IsEnabledClock()
2902 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs) in LL_APB4_GRP1_DisableClock() argument
2904 CLEAR_BIT(RCC->APB4ENR, Periphs); in LL_APB4_GRP1_DisableClock()
2942 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs) in LL_APB4_GRP1_ForceReset() argument
2944 SET_BIT(RCC->APB4RSTR, Periphs); in LL_APB4_GRP1_ForceReset()
2982 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs) in LL_APB4_GRP1_ReleaseReset() argument
2984 CLEAR_BIT(RCC->APB4RSTR, Periphs); in LL_APB4_GRP1_ReleaseReset()
3024 __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs) in LL_APB4_GRP1_EnableClockSleep() argument
3027 SET_BIT(RCC->APB4LPENR, Periphs); in LL_APB4_GRP1_EnableClockSleep()
3029 tmpreg = READ_BIT(RCC->APB4LPENR, Periphs); in LL_APB4_GRP1_EnableClockSleep()
3070 __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs) in LL_APB4_GRP1_DisableClockSleep() argument
3072 CLEAR_BIT(RCC->APB4LPENR, Periphs); in LL_APB4_GRP1_DisableClockSleep()
3129 __STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs) in LL_CLKAM_Enable() argument
3134 SET_BIT(RCC->D3AMR, Periphs); in LL_CLKAM_Enable()
3136 tmpreg = READ_BIT(RCC->D3AMR, Periphs); in LL_CLKAM_Enable()
3138 SET_BIT(RCC->SRDAMR, Periphs); in LL_CLKAM_Enable()
3140 tmpreg = READ_BIT(RCC->SRDAMR, Periphs); in LL_CLKAM_Enable()
3191 __STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs) in LL_CLKAM_Disable() argument
3194 CLEAR_BIT(RCC->D3AMR, Periphs); in LL_CLKAM_Disable()
3196 CLEAR_BIT(RCC->SRDAMR, Periphs); in LL_CLKAM_Disable()
3258 __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs) in LL_CKGA_Enable() argument
3261 SET_BIT(RCC->CKGAENR, Periphs); in LL_CKGA_Enable()
3263 tmpreg = READ_BIT(RCC->CKGAENR, Periphs); in LL_CKGA_Enable()
3318 __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs) in LL_CKGA_Disable() argument
3320 CLEAR_BIT(RCC->CKGAENR, Periphs); in LL_CKGA_Disable()
3365 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs) in LL_C1_AHB3_GRP1_EnableClock() argument
3368 SET_BIT(RCC_C1->AHB3ENR, Periphs); in LL_C1_AHB3_GRP1_EnableClock()
3370 tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs); in LL_C1_AHB3_GRP1_EnableClock()
3405 __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C1_AHB3_GRP1_IsEnabledClock() argument
3407 return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_AHB3_GRP1_IsEnabledClock()
3441 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs) in LL_C1_AHB3_GRP1_DisableClock() argument
3443 CLEAR_BIT(RCC_C1->AHB3ENR, Periphs); in LL_C1_AHB3_GRP1_DisableClock()
3486 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C1_AHB3_GRP1_EnableClockSleep() argument
3489 SET_BIT(RCC_C1->AHB3LPENR, Periphs); in LL_C1_AHB3_GRP1_EnableClockSleep()
3491 tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs); in LL_C1_AHB3_GRP1_EnableClockSleep()
3535 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C1_AHB3_GRP1_DisableClockSleep() argument
3537 CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs); in LL_C1_AHB3_GRP1_DisableClockSleep()
3579 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_C1_AHB1_GRP1_EnableClock() argument
3582 SET_BIT(RCC_C1->AHB1ENR, Periphs); in LL_C1_AHB1_GRP1_EnableClock()
3584 tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs); in LL_C1_AHB1_GRP1_EnableClock()
3619 __STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C1_AHB1_GRP1_IsEnabledClock() argument
3621 return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_AHB1_GRP1_IsEnabledClock()
3655 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_C1_AHB1_GRP1_DisableClock() argument
3657 CLEAR_BIT(RCC_C1->AHB1ENR, Periphs); in LL_C1_AHB1_GRP1_DisableClock()
3691 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C1_AHB1_GRP1_EnableClockSleep() argument
3694 SET_BIT(RCC_C1->AHB1LPENR, Periphs); in LL_C1_AHB1_GRP1_EnableClockSleep()
3696 tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs); in LL_C1_AHB1_GRP1_EnableClockSleep()
3731 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C1_AHB1_GRP1_DisableClockSleep() argument
3733 CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs); in LL_C1_AHB1_GRP1_DisableClockSleep()
3771 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs) in LL_C1_AHB2_GRP1_EnableClock() argument
3774 SET_BIT(RCC_C1->AHB2ENR, Periphs); in LL_C1_AHB2_GRP1_EnableClock()
3776 tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs); in LL_C1_AHB2_GRP1_EnableClock()
3807 __STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C1_AHB2_GRP1_IsEnabledClock() argument
3809 return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_AHB2_GRP1_IsEnabledClock()
3839 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs) in LL_C1_AHB2_GRP1_DisableClock() argument
3841 CLEAR_BIT(RCC_C1->AHB2ENR, Periphs); in LL_C1_AHB2_GRP1_DisableClock()
3869 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C1_AHB2_GRP1_EnableClockSleep() argument
3872 SET_BIT(RCC_C1->AHB2LPENR, Periphs); in LL_C1_AHB2_GRP1_EnableClockSleep()
3874 tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs); in LL_C1_AHB2_GRP1_EnableClockSleep()
3903 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C1_AHB2_GRP1_DisableClockSleep() argument
3905 CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs); in LL_C1_AHB2_GRP1_DisableClockSleep()
3957 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs) in LL_C1_AHB4_GRP1_EnableClock() argument
3960 SET_BIT(RCC_C1->AHB4ENR, Periphs); in LL_C1_AHB4_GRP1_EnableClock()
3962 tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs); in LL_C1_AHB4_GRP1_EnableClock()
4007 __STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C1_AHB4_GRP1_IsEnabledClock() argument
4009 return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_AHB4_GRP1_IsEnabledClock()
4053 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs) in LL_C1_AHB4_GRP1_DisableClock() argument
4055 CLEAR_BIT(RCC_C1->AHB4ENR, Periphs); in LL_C1_AHB4_GRP1_DisableClock()
4095 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C1_AHB4_GRP1_EnableClockSleep() argument
4098 SET_BIT(RCC_C1->AHB4LPENR, Periphs); in LL_C1_AHB4_GRP1_EnableClockSleep()
4100 tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs); in LL_C1_AHB4_GRP1_EnableClockSleep()
4141 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C1_AHB4_GRP1_DisableClockSleep() argument
4143 CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs); in LL_C1_AHB4_GRP1_DisableClockSleep()
4167 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs) in LL_C1_APB3_GRP1_EnableClock() argument
4170 SET_BIT(RCC_C1->APB3ENR, Periphs); in LL_C1_APB3_GRP1_EnableClock()
4172 tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs); in LL_C1_APB3_GRP1_EnableClock()
4189 __STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C1_APB3_GRP1_IsEnabledClock() argument
4191 return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_APB3_GRP1_IsEnabledClock()
4208 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs) in LL_C1_APB3_GRP1_DisableClock() argument
4210 CLEAR_BIT(RCC_C1->APB3ENR, Periphs); in LL_C1_APB3_GRP1_DisableClock()
4226 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C1_APB3_GRP1_EnableClockSleep() argument
4229 SET_BIT(RCC_C1->APB3LPENR, Periphs); in LL_C1_APB3_GRP1_EnableClockSleep()
4231 tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs); in LL_C1_APB3_GRP1_EnableClockSleep()
4248 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C1_APB3_GRP1_DisableClockSleep() argument
4250 CLEAR_BIT(RCC_C1->APB3LPENR, Periphs); in LL_C1_APB3_GRP1_DisableClockSleep()
4318 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs) in LL_C1_APB1_GRP1_EnableClock() argument
4321 SET_BIT(RCC_C1->APB1LENR, Periphs); in LL_C1_APB1_GRP1_EnableClock()
4323 tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs); in LL_C1_APB1_GRP1_EnableClock()
4384 __STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C1_APB1_GRP1_IsEnabledClock() argument
4386 return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_APB1_GRP1_IsEnabledClock()
4446 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs) in LL_C1_APB1_GRP1_DisableClock() argument
4448 CLEAR_BIT(RCC_C1->APB1LENR, Periphs); in LL_C1_APB1_GRP1_DisableClock()
4508 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C1_APB1_GRP1_EnableClockSleep() argument
4511 SET_BIT(RCC_C1->APB1LLPENR, Periphs); in LL_C1_APB1_GRP1_EnableClockSleep()
4513 tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs); in LL_C1_APB1_GRP1_EnableClockSleep()
4574 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C1_APB1_GRP1_DisableClockSleep() argument
4576 CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs); in LL_C1_APB1_GRP1_DisableClockSleep()
4598 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs) in LL_C1_APB1_GRP2_EnableClock() argument
4601 SET_BIT(RCC_C1->APB1HENR, Periphs); in LL_C1_APB1_GRP2_EnableClock()
4603 tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs); in LL_C1_APB1_GRP2_EnableClock()
4626 __STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs) in LL_C1_APB1_GRP2_IsEnabledClock() argument
4628 return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_APB1_GRP2_IsEnabledClock()
4650 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs) in LL_C1_APB1_GRP2_DisableClock() argument
4652 CLEAR_BIT(RCC_C1->APB1HENR, Periphs); in LL_C1_APB1_GRP2_DisableClock()
4674 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs) in LL_C1_APB1_GRP2_EnableClockSleep() argument
4677 SET_BIT(RCC_C1->APB1HLPENR, Periphs); in LL_C1_APB1_GRP2_EnableClockSleep()
4679 tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs); in LL_C1_APB1_GRP2_EnableClockSleep()
4702 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs) in LL_C1_APB1_GRP2_DisableClockSleep() argument
4704 CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs); in LL_C1_APB1_GRP2_DisableClockSleep()
4756 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs) in LL_C1_APB2_GRP1_EnableClock() argument
4759 SET_BIT(RCC_C1->APB2ENR, Periphs); in LL_C1_APB2_GRP1_EnableClock()
4761 tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs); in LL_C1_APB2_GRP1_EnableClock()
4806 __STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C1_APB2_GRP1_IsEnabledClock() argument
4808 return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_APB2_GRP1_IsEnabledClock()
4852 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs) in LL_C1_APB2_GRP1_DisableClock() argument
4854 CLEAR_BIT(RCC_C1->APB2ENR, Periphs); in LL_C1_APB2_GRP1_DisableClock()
4898 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C1_APB2_GRP1_EnableClockSleep() argument
4901 SET_BIT(RCC_C1->APB2LPENR, Periphs); in LL_C1_APB2_GRP1_EnableClockSleep()
4903 tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs); in LL_C1_APB2_GRP1_EnableClockSleep()
4948 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C1_APB2_GRP1_DisableClockSleep() argument
4950 CLEAR_BIT(RCC_C1->APB2LPENR, Periphs); in LL_C1_APB2_GRP1_DisableClockSleep()
4997 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs) in LL_C1_APB4_GRP1_EnableClock() argument
5000 SET_BIT(RCC_C1->APB4ENR, Periphs); in LL_C1_APB4_GRP1_EnableClock()
5002 tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs); in LL_C1_APB4_GRP1_EnableClock()
5040 __STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C1_APB4_GRP1_IsEnabledClock() argument
5042 return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C1_APB4_GRP1_IsEnabledClock()
5080 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs) in LL_C1_APB4_GRP1_DisableClock() argument
5082 CLEAR_BIT(RCC_C1->APB4ENR, Periphs); in LL_C1_APB4_GRP1_DisableClock()
5120 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C1_APB4_GRP1_EnableClockSleep() argument
5123 SET_BIT(RCC_C1->APB4LPENR, Periphs); in LL_C1_APB4_GRP1_EnableClockSleep()
5125 tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs); in LL_C1_APB4_GRP1_EnableClockSleep()
5164 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C1_APB4_GRP1_DisableClockSleep() argument
5166 CLEAR_BIT(RCC_C1->APB4LPENR, Periphs); in LL_C1_APB4_GRP1_DisableClockSleep()
5204 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) in LL_C2_AHB3_GRP1_EnableClock() argument
5207 SET_BIT(RCC_C2->AHB3ENR, Periphs); in LL_C2_AHB3_GRP1_EnableClock()
5209 tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs); in LL_C2_AHB3_GRP1_EnableClock()
5240 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C2_AHB3_GRP1_IsEnabledClock() argument
5242 return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C2_AHB3_GRP1_IsEnabledClock()
5272 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs) in LL_C2_AHB3_GRP1_DisableClock() argument
5274 CLEAR_BIT(RCC_C2->AHB3ENR, Periphs); in LL_C2_AHB3_GRP1_DisableClock()
5303 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C2_AHB3_GRP1_EnableClockSleep() argument
5306 SET_BIT(RCC_C2->AHB3LPENR, Periphs); in LL_C2_AHB3_GRP1_EnableClockSleep()
5308 tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs); in LL_C2_AHB3_GRP1_EnableClockSleep()
5338 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C2_AHB3_GRP1_DisableClockSleep() argument
5340 CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs); in LL_C2_AHB3_GRP1_DisableClockSleep()
5380 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs) in LL_C2_AHB1_GRP1_EnableClock() argument
5383 SET_BIT(RCC_C2->AHB1ENR, Periphs); in LL_C2_AHB1_GRP1_EnableClock()
5385 tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs); in LL_C2_AHB1_GRP1_EnableClock()
5418 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C2_AHB1_GRP1_IsEnabledClock() argument
5420 return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C2_AHB1_GRP1_IsEnabledClock()
5452 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs) in LL_C2_AHB1_GRP1_DisableClock() argument
5454 CLEAR_BIT(RCC_C2->AHB1ENR, Periphs); in LL_C2_AHB1_GRP1_DisableClock()
5486 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C2_AHB1_GRP1_EnableClockSleep() argument
5489 SET_BIT(RCC_C2->AHB1LPENR, Periphs); in LL_C2_AHB1_GRP1_EnableClockSleep()
5491 tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs); in LL_C2_AHB1_GRP1_EnableClockSleep()
5524 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C2_AHB1_GRP1_DisableClockSleep() argument
5526 CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs); in LL_C2_AHB1_GRP1_DisableClockSleep()
5554 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs) in LL_C2_AHB2_GRP1_EnableClock() argument
5557 SET_BIT(RCC_C2->AHB2ENR, Periphs); in LL_C2_AHB2_GRP1_EnableClock()
5559 tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs); in LL_C2_AHB2_GRP1_EnableClock()
5580 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C2_AHB2_GRP1_IsEnabledClock() argument
5582 return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C2_AHB2_GRP1_IsEnabledClock()
5602 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs) in LL_C2_AHB2_GRP1_DisableClock() argument
5604 CLEAR_BIT(RCC_C2->AHB2ENR, Periphs); in LL_C2_AHB2_GRP1_DisableClock()
5630 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C2_AHB2_GRP1_EnableClockSleep() argument
5633 SET_BIT(RCC_C2->AHB2LPENR, Periphs); in LL_C2_AHB2_GRP1_EnableClockSleep()
5635 tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs); in LL_C2_AHB2_GRP1_EnableClockSleep()
5662 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C2_AHB2_GRP1_DisableClockSleep() argument
5664 CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs); in LL_C2_AHB2_GRP1_DisableClockSleep()
5716 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs) in LL_C2_AHB4_GRP1_EnableClock() argument
5719 SET_BIT(RCC_C2->AHB4ENR, Periphs); in LL_C2_AHB4_GRP1_EnableClock()
5721 tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs); in LL_C2_AHB4_GRP1_EnableClock()
5766 __STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C2_AHB4_GRP1_IsEnabledClock() argument
5768 return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C2_AHB4_GRP1_IsEnabledClock()
5812 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs) in LL_C2_AHB4_GRP1_DisableClock() argument
5814 CLEAR_BIT(RCC_C2->AHB4ENR, Periphs); in LL_C2_AHB4_GRP1_DisableClock()
5854 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C2_AHB4_GRP1_EnableClockSleep() argument
5857 SET_BIT(RCC_C2->AHB4LPENR, Periphs); in LL_C2_AHB4_GRP1_EnableClockSleep()
5859 tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs); in LL_C2_AHB4_GRP1_EnableClockSleep()
5900 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C2_AHB4_GRP1_DisableClockSleep() argument
5902 CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs); in LL_C2_AHB4_GRP1_DisableClockSleep()
5926 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs) in LL_C2_APB3_GRP1_EnableClock() argument
5929 SET_BIT(RCC_C2->APB3ENR, Periphs); in LL_C2_APB3_GRP1_EnableClock()
5931 tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs); in LL_C2_APB3_GRP1_EnableClock()
5948 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C2_APB3_GRP1_IsEnabledClock() argument
5950 return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C2_APB3_GRP1_IsEnabledClock()
5966 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs) in LL_C2_APB3_GRP1_DisableClock() argument
5968 CLEAR_BIT(RCC_C2->APB3ENR, Periphs); in LL_C2_APB3_GRP1_DisableClock()
5984 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C2_APB3_GRP1_EnableClockSleep() argument
5987 SET_BIT(RCC_C2->APB3LPENR, Periphs); in LL_C2_APB3_GRP1_EnableClockSleep()
5989 tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs); in LL_C2_APB3_GRP1_EnableClockSleep()
6006 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C2_APB3_GRP1_DisableClockSleep() argument
6008 CLEAR_BIT(RCC_C2->APB3LPENR, Periphs); in LL_C2_APB3_GRP1_DisableClockSleep()
6076 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs) in LL_C2_APB1_GRP1_EnableClock() argument
6079 SET_BIT(RCC_C2->APB1LENR, Periphs); in LL_C2_APB1_GRP1_EnableClock()
6081 tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs); in LL_C2_APB1_GRP1_EnableClock()
6142 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C2_APB1_GRP1_IsEnabledClock() argument
6144 return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs) ? 1U : 0U); in LL_C2_APB1_GRP1_IsEnabledClock()
6204 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs) in LL_C2_APB1_GRP1_DisableClock() argument
6206 CLEAR_BIT(RCC_C2->APB1LENR, Periphs); in LL_C2_APB1_GRP1_DisableClock()
6266 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C2_APB1_GRP1_EnableClockSleep() argument
6269 SET_BIT(RCC_C2->APB1LLPENR, Periphs); in LL_C2_APB1_GRP1_EnableClockSleep()
6271 tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs); in LL_C2_APB1_GRP1_EnableClockSleep()
6332 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C2_APB1_GRP1_DisableClockSleep() argument
6334 CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs); in LL_C2_APB1_GRP1_DisableClockSleep()
6356 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs) in LL_C2_APB1_GRP2_EnableClock() argument
6359 SET_BIT(RCC_C2->APB1HENR, Periphs); in LL_C2_APB1_GRP2_EnableClock()
6361 tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs); in LL_C2_APB1_GRP2_EnableClock()
6384 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs) in LL_C2_APB1_GRP2_IsEnabledClock() argument
6386 return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs) ? 1U : 0U); in LL_C2_APB1_GRP2_IsEnabledClock()
6408 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs) in LL_C2_APB1_GRP2_DisableClock() argument
6410 CLEAR_BIT(RCC_C2->APB1HENR, Periphs); in LL_C2_APB1_GRP2_DisableClock()
6432 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs) in LL_C2_APB1_GRP2_EnableClockSleep() argument
6435 SET_BIT(RCC_C2->APB1HLPENR, Periphs); in LL_C2_APB1_GRP2_EnableClockSleep()
6437 tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs); in LL_C2_APB1_GRP2_EnableClockSleep()
6460 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs) in LL_C2_APB1_GRP2_DisableClockSleep() argument
6462 CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs); in LL_C2_APB1_GRP2_DisableClockSleep()
6511 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs) in LL_C2_APB2_GRP1_EnableClock() argument
6514 SET_BIT(RCC_C2->APB2ENR, Periphs); in LL_C2_APB2_GRP1_EnableClock()
6516 tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs); in LL_C2_APB2_GRP1_EnableClock()
6557 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C2_APB2_GRP1_IsEnabledClock() argument
6559 return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C2_APB2_GRP1_IsEnabledClock()
6599 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs) in LL_C2_APB2_GRP1_DisableClock() argument
6601 CLEAR_BIT(RCC_C2->APB2ENR, Periphs); in LL_C2_APB2_GRP1_DisableClock()
6641 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C2_APB2_GRP1_EnableClockSleep() argument
6644 SET_BIT(RCC_C2->APB2LPENR, Periphs); in LL_C2_APB2_GRP1_EnableClockSleep()
6646 tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs); in LL_C2_APB2_GRP1_EnableClockSleep()
6687 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C2_APB2_GRP1_DisableClockSleep() argument
6689 CLEAR_BIT(RCC_C2->APB2LPENR, Periphs); in LL_C2_APB2_GRP1_DisableClockSleep()
6731 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs) in LL_C2_APB4_GRP1_EnableClock() argument
6734 SET_BIT(RCC_C2->APB4ENR, Periphs); in LL_C2_APB4_GRP1_EnableClock()
6736 tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs); in LL_C2_APB4_GRP1_EnableClock()
6771 __STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs) in LL_C2_APB4_GRP1_IsEnabledClock() argument
6773 return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs) ? 1U : 0U); in LL_C2_APB4_GRP1_IsEnabledClock()
6807 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs) in LL_C2_APB4_GRP1_DisableClock() argument
6809 CLEAR_BIT(RCC_C2->APB4ENR, Periphs); in LL_C2_APB4_GRP1_DisableClock()
6843 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs) in LL_C2_APB4_GRP1_EnableClockSleep() argument
6846 SET_BIT(RCC_C2->APB4LPENR, Periphs); in LL_C2_APB4_GRP1_EnableClockSleep()
6848 tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs); in LL_C2_APB4_GRP1_EnableClockSleep()
6883 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs) in LL_C2_APB4_GRP1_DisableClockSleep() argument
6885 CLEAR_BIT(RCC_C2->APB4LPENR, Periphs); in LL_C2_APB4_GRP1_DisableClockSleep()