Lines Matching refs:APB2ENR
2176 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
2178 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
2184 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2186 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2192 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
2194 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
2200 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
2202 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
2209 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
2211 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
2219 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
2221 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
2228 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2230 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2236 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2238 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2244 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
2246 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
2252 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
2254 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
2260 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
2262 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
2268 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
2270 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
2276 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
2278 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
2285 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
2287 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
2295 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
2297 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
2304 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
2306 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
2313 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
2315 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
2320 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
2321 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
2322 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
2323 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
2325 #define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)
2328 #define __HAL_RCC_USART10_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)
2330 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
2331 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
2332 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
2333 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
2334 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
2335 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
2336 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
2338 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
2341 #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
2343 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
2345 #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
2354 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U)
2355 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U)
2356 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
2357 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)
2359 #define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)
2362 #define __HAL_RCC_USART10_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)
2364 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U)
2365 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U)
2366 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U)
2367 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U)
2368 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U)
2369 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)
2370 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U)
2372 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U)
2375 #define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U)
2377 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)
2379 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U)
2382 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U)
2383 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U)
2384 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
2385 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)
2387 #define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)
2390 #define __HAL_RCC_USART10_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)
2392 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U)
2393 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U)
2394 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U)
2395 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U)
2396 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U)
2397 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)
2398 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U)
2400 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U)
2403 #define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U)
2405 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)
2407 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U)
3376 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
3378 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
3384 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
3386 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
3392 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
3394 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
3400 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
3402 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
3408 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
3410 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
3416 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
3418 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
3424 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
3426 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
3432 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
3434 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
3440 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
3442 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
3448 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
3450 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
3456 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
3458 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
3464 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
3466 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
3472 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
3474 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
3480 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
3482 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
3488 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
3490 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
3494 #define __HAL_RCC_C1_TIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
3495 #define __HAL_RCC_C1_TIM8_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
3496 #define __HAL_RCC_C1_USART1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
3497 #define __HAL_RCC_C1_USART6_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
3498 #define __HAL_RCC_C1_SPI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
3499 #define __HAL_RCC_C1_SPI4_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
3500 #define __HAL_RCC_C1_TIM15_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
3501 #define __HAL_RCC_C1_TIM16_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
3502 #define __HAL_RCC_C1_TIM17_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
3503 #define __HAL_RCC_C1_SPI5_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
3504 #define __HAL_RCC_C1_SAI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
3505 #define __HAL_RCC_C1_SAI2_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
3506 #define __HAL_RCC_C1_SAI3_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
3507 #define __HAL_RCC_C1_DFSDM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
3508 #define __HAL_RCC_C1_HRTIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
4406 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
4408 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
4414 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
4416 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
4422 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
4424 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
4430 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
4432 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
4438 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
4440 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
4446 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
4448 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
4454 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
4456 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
4462 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
4464 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
4470 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
4472 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
4478 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
4480 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
4486 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
4488 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
4494 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
4496 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
4502 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
4504 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
4510 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
4512 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
4518 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
4520 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
4524 #define __HAL_RCC_C2_TIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
4525 #define __HAL_RCC_C2_TIM8_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
4526 #define __HAL_RCC_C2_USART1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
4527 #define __HAL_RCC_C2_USART6_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
4528 #define __HAL_RCC_C2_SPI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
4529 #define __HAL_RCC_C2_SPI4_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
4530 #define __HAL_RCC_C2_TIM15_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
4531 #define __HAL_RCC_C2_TIM16_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
4532 #define __HAL_RCC_C2_TIM17_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
4533 #define __HAL_RCC_C2_SPI5_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
4534 #define __HAL_RCC_C2_SAI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
4535 #define __HAL_RCC_C2_SAI2_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
4536 #define __HAL_RCC_C2_SAI3_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
4537 #define __HAL_RCC_C2_DFSDM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
4538 #define __HAL_RCC_C2_HRTIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)