Lines Matching refs:AHB3RSTR

4663 #define __HAL_RCC_AHB3_FORCE_RESET()          (RCC->AHB3RSTR = 0x00015031U)  /* Resets MDMA, DMA2D,…
4665 #define __HAL_RCC_AHB3_FORCE_RESET()          (RCC->AHB3RSTR = 0x01E95031U)  /* Resets MDMA, DMA2D,…
4667 #define __HAL_RCC_AHB3_FORCE_RESET()          (RCC->AHB3RSTR = 0x00E95011U)  /* Resets MDMA, DMA2D,…
4669 #define __HAL_RCC_MDMA_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
4670 #define __HAL_RCC_DMA2D_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
4672 #define __HAL_RCC_JPGDECRST_FORCE_RESET()     (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
4674 #define __HAL_RCC_FMC_FORCE_RESET()           (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
4676 #define __HAL_RCC_QSPI_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
4679 #define __HAL_RCC_OSPI1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))
4681 #define __HAL_RCC_SDMMC1_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
4683 #define __HAL_RCC_OSPI2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))
4686 #define __HAL_RCC_IOMNGR_FORCE_RESET()      (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))
4689 #define __HAL_RCC_OTFDEC1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))
4692 #define __HAL_RCC_OTFDEC2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))
4695 #define __HAL_RCC_GFXMMU_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))
4698 #define __HAL_RCC_AHB3_RELEASE_RESET()        (RCC->AHB3RSTR = 0x00)
4699 #define __HAL_RCC_MDMA_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
4700 #define __HAL_RCC_DMA2D_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
4702 #define __HAL_RCC_JPGDECRST_RELEASE_RESET()   (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
4704 #define __HAL_RCC_FMC_RELEASE_RESET()         (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
4706 #define __HAL_RCC_QSPI_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
4709 #define __HAL_RCC_OSPI1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))
4711 #define __HAL_RCC_SDMMC1_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
4713 #define __HAL_RCC_OSPI2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))
4716 #define __HAL_RCC_IOMNGR_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))
4719 #define __HAL_RCC_OTFDEC1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))
4722 #define __HAL_RCC_OTFDEC2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))
4725 #define __HAL_RCC_GFXMMU_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))