Lines Matching +full:fail +full:- +full:fast
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M7 Specific Interrupt Numbers =============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preemp…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access V…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other a…
61 …UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State …
62 …SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction …
63 …DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor …
64 …PendSV_IRQn = -2, /*!< -2 Pendable request for system service …
65 …SysTick_IRQn = -1, /*!< -1 System Tick Timer …
189 …WAKEUP_PIN_IRQn = 132, /*!< Wake-up pins interrupt …
218 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
220 #define __CM7_REV 0x0102U /*!< Cortex-M7 revision r1p2 */
232 #include <core_cm7.h> /*!< ARM Cortex-M7 processor and core peripherals */
271 … uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
276 … uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
281 … uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
288 … uint32_t RESERVED10[4];/*!< Reserved, 0x0B8 - 0x0BC */
305 …uint32_t RESERVED1[9]; /*!< Reserved, Address offset: 0x00-0x20 …
307 …uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x28-0xFC …
315 …uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x00-0x04 …
317 …uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x0C-0x20 …
321 …uint32_t RESERVED5[54]; /*!< Reserved, Address offset: 0x30-0x104…
370 …RVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */
372 …RVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */
379 …RVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */
385 …RVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */
388 …RVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */
393 …RVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */
396 …__IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset…
397 …VED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */
450 …__IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address o…
451 …__IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address o…
452 …__IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address o…
453 …__IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address o…
479 …SERVED1[5]; /*!< Reserved, Address offset: 0x08-0x18 */
483 …SERVED3[5]; /*!< Reserved, Address offset: 0x28-0x38 */
485 …SERVED4[3]; /*!< Reserved, Address offset: 0x40-0x48 */
489 …SERVED6[41]; /*!< Reserved, Address offset: 0x58-0xF8 */
494 …RVED7[945]; /*!< Reserved, Address offset: 0x10C-0xFCC */
496 …RVED8[3]; /*!< Reserved, Address offset: 0xFD4-0xFDC */
512 …__IO uint32_t IPGR1; /*!< IP-Plug global register 1 Address offset…
513 …__IO uint32_t IPGR2; /*!< IP-Plug global register 2 Address offset…
514 …__IO uint32_t IPGR3; /*!< IP-Plug global register 3 Address offset…
515 … RESERVED1[4]; /*!< Reserved, Address offset: 0x0C-0x18 */
516 …__IO uint32_t IPGR8; /*!< IP-Plug global register 8 Address offset…
517 …__IO uint32_t IPC1R1; /*!< IP-Plug client 1 register 1 Address offset…
518 …__IO uint32_t IPC1R2; /*!< IP-Plug client 1 register 2 Address offset…
519 …__IO uint32_t IPC1R3; /*!< IP-Plug client 1 register 3 Address offset…
520 …t32_t RESERVED2[54]; /*!< Reserved, Address offset: 0x2C-0x100 */
524 …t32_t RESERVED3[57]; /*!< Reserved, Address offset: 0x110-0x1F0 */
531 …t32_t RESERVED5[121]; /*!< Reserved, Address offset: 0x20C-0x3EC */
538 …t32_t RESERVED7[62]; /*!< Reserved, Address offset: 0x408-0x4FC */
542 …t32_t RESERVED8[41]; /*!< Reserved, Address offset: 0x50C-0x5AC */
545 …t32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x5B8-0x5BC */
549 …t32_t RESERVED10[10]; /*!< Reserved, Address offset: 0x5CC-0x5F0 */
553 …t32_t RESERVED11[64]; /*!< Reserved, Address offset: 0x600-0x6FC */
557 …t32_t RESERVED12[45]; /*!< Reserved, Address offset: 0x70C-0x7BC */
585 …__IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset:…
586 …ED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */
590 …ED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */
598 …ED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */
599 …__IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset:…
627 …uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0…
628 …__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0…
629 …__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0…
833 …t32_t RESERVED1[5]; /*!< Reserved 1, Address offset: 0x0C-0x1C */
837 …t32_t RESERVED2[21]; /*!< Reserved 2, Address offset: 0x2C-0x7C */
867 …32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
876 …32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
885 …32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
905 …SERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
907 …SERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */
921 …[2]; /*!< Reserved, Address offset: 0x008 - 0x00C */
924 …[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */
933 …__IO uint32_t ECCSFADDR; /*!< FLASH ECC single fail address register, Address …
934 …__IO uint32_t ECCDFADDR; /*!< FLASH ECC double fail address register, Address …
935 …[46]; /*!< Reserved, Address offset: 0x048 - 0x0FC */
942 … /*!< FLASH option bytes key data register, Address offset: 0x118 - 0x134 */
943 …[50]; /*!< Reserved, Address offset: 0x138 - 0x1FC */
944 …__IO uint32_t NVSR; /*!< FLASH non-volatile status register, Address …
952 …[4]; /*!< Reserved, Address offset: 0x220 - 0x22C */
955 …[6]; /*!< Reserved, Address offset: 0x238 - 0x24C */
958 …[2]; /*!< Reserved, Address offset: 0x258 - 0x25C */
969 …CR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
976 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
996 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140 - 0x144 */
997 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148 - 0x14C */
1011 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C …
1016 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24…
1049 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1052 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1053 …__IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */
1061 …__IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C …
1065 * @brief Inter-integrated Circuit Interface
1084 * @brief Improved Inter-integrated Circuit Interface
1091 …t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */
1098 …t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */
1101 …t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */
1103 …t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */
1109 …nt32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */
1110 …t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */
1113 …t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */
1117 …t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */
1153 …ESERVED0[4]; /* Reserved Address offset: 0x20-0x2C */
1160 …ESERVED2[2]; /* Reserved Address offset: 0x48-0x4C */
1161 …MEM0[16]; /*!< JPEG quantization tables 0, Address offset: 0x50-0x8C */
1162 …MEM1[16]; /*!< JPEG quantization tables 1, Address offset: 0x90-0xCC */
1163 …EM2[16]; /*!< JPEG quantization tables 2, Address offset: 0xD0-0x10C */
1164 …M3[16]; /*!< JPEG quantization tables 3, Address offset: 0x110-0x14C */
1165 …FMIN[16]; /*!< JPEG HuffMin tables, Address offset: 0x150-0x18C */
1166 …FBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 0x190-0x20C */
1167 …FSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 0x210-0x35C */
1168 …MEM[103]; /*!< JPEG DHTMem tables, Address offset: 0x360-0x4F8 */
1170 …FENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 0x500-0x65C */
1171 …FENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 0x660-0x7BC */
1172 …FENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 0x7C0-0x7DC */
1173 …FENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 0x7E0-0x7FC */
1202 …MCE region configuration register, Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */
1203 …MCE region start address register, Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */
1204 …MCE region end address register, Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */
1205 …MCE region attribute register, Address offset: 0x04C + 0x10 * (x-1) (x = 1 to 4) */
1210 …MCE cipher context configuration register, Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */
1211 …MCE cipher context nonce register 0, Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */
1212 …MCE cipher context nonce register 1, Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */
1213 …MCE cipher context key register 0, Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */
1214 …MCE cipher context key register 1, Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */
1215 …MCE cipher context key register 2, Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */
1216 …MCE cipher context key register 3, Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */
1226 … /*!< Reserved, Address offset: 0x014-0x018 */
1230 …]; /*!< Reserved, Address offset: 0x028-0x1FC */
1235 … /*!< Reserved, Address offset: 0x210-0x21C */
1236 …__IO uint32_t FMKEYR0; /*!< MCE fast master key register 0, Address…
1237 …__IO uint32_t FMKEYR1; /*!< MCE fast master key register 1, Address…
1238 …__IO uint32_t FMKEYR2; /*!< MCE fast master key register 2, Address…
1239 …__IO uint32_t FMKEYR3; /*!< MCE fast master key register 3, Address…
1341 …uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 …
1351 …uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC …
1366 …2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */
1369 …3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */
1375 …6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */
1381 …9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */
1387 …12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */
1389 …13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */
1390 …__IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address o…
1391 …14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */
1397 …17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */
1399 …18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */
1405 …21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */
1407 …22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */
1409 …23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */
1410 …__IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address o…
1443 …__IO uint32_t UCPDR; /*!< PWR USB Type-C and power delivery register, Address offset: 0x…
1445 …__IO uint32_t PUCRN; /*!< PWR port N pull-up control register, Address offset: 0x…
1446 …__IO uint32_t PDCRN; /*!< PWR port N pull-down control register, Address offset: 0x…
1447 …__IO uint32_t PUCRO; /*!< PWR port O pull-up control register, Address offset: 0x…
1448 …__IO uint32_t PDCRO; /*!< PWR port O pull-down control register, Address offset: 0x…
1449 …__IO uint32_t PDCRP; /*!< PWR port P pull-down control register, Address offset: 0x…
1463 …uint32_t Reserved1[253]; /*!< Reserved, Address offset: 0x000C-0x03F…
1464 …__IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x0400-0x18D…
1478 __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x018 - 0x024 */
1549 …served, Address offset: 0xA8-0xAC */
1551 …served, Address offset: 0xB4-0xBC */
1558 …served, Address offset: 0xD8-0xFC */
1560 …erved, Address offset: 0x104-0x12C */
1603 * @brief Real-Time Clock
1621 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x…
1665 … RESERVED1[168]; /*!< Reserved, Address offset: 0x60 -- 0x2FC */
1700 …ERVED1[3]; /*!< Reserved, Address offset: 0x04-0x0C */
1703 …ERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */
1706 …ERVED3[3]; /*!< Reserved, Address offset: 0x28-0x30 */
1708 …ERVED4[50]; /*!< Reserved, Address offset: 0x38-0xFC */
1718 …VED7[3]; /*!< Reserved, Address offset: 0x124-0x12C */
1719 …R[4]; /*!< SBS External Interrupt Configuration registers, Address offset: 0x130-0x13C */
1744 …t RESERVED0[3]; /*!< Reserved, Address offset : 0x044 - 0x04C */
1748 …t RESERVED1[2]; /*!< Reserved, Address offset : 0x05C - 0x060 */
1751 …t RESERVED2[5]; /*!< Reserved, Address offset : 0x06C - 0x07C */
1756 * @brief SPDIF-RX Interface
1783 …uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24-0x2C…
1785 …uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34-0x3C…
1815 …SERVED4[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */
1817 …SERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */
1868 …__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C …
1874 …__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 …
1968 uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */
1974 * @brief USB_OTG_IN_Endpoint-Specific_Register
1989 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2074 #define SRAM1_AXI_BASE 0x24000000UL /*!< SRAM1 base address - accessible over AXI…
2075 #define SRAM2_AXI_BASE 0x24020000UL /*!< SRAM2 base address - accessible over AXI…
2076 #define SRAM3_AXI_BASE 0x24040000UL /*!< SRAM3 base address - accessible over AXI…
2077 #define SRAM4_AXI_BASE 0x24060000UL /*!< SRAM4 base address - accessible over AXI…
2426 * &(FLASH->WRPSRP), &(FLASH->HDPSRP) or &(FLASH->ROTSRP)
3514 … ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
3538 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
3787 /* HDMI-CEC (CEC) */
3844 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Rec…
3850 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun …
3874 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer U…
3877 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error …
3885 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Rec…
3891 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun …
3915 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer U…
3918 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT…
3999 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data regist…
4701 …_CLASS_Msk /*!< Component ID field, bits [15:12] - component class */
4731 …IPGR2_PSTART DCMIPP_IPGR2_PSTART_Msk /*!< request to lock the IP-Plug */
4736 …IPGR3_IDLE DCMIPP_IPGR3_IDLE_Msk /*!< request to lock the IP-Plug */
4870 #define DCMIPP_CMIER_P0LINEIE DCMIPP_CMIER_P0LINEIE_Msk /*!< multi-Line Capt…
4904 #define DCMIPP_CMSR2_P0LINEF DCMIPP_CMSR2_P0LINEF_Msk /*!< multi-Line Capt…
4927 #define DCMIPP_CMFCR_CP0LINEF DCMIPP_CMFCR_CP0LINEF_Msk /*!< multi-Line Capt…
5028 #define DCMIPP_P0IER_LINEIE DCMIPP_P0IER_LINEIE_Msk /*!< multi-Line Capt…
5045 #define DCMIPP_P0SR_LINEF DCMIPP_P0SR_LINEF_Msk /*!< multi-Line Capt…
5068 #define DCMIPP_P0FCR_CLINEF DCMIPP_P0FCR_CLINEF_Msk /*!< multi-Line Capt…
5361 #define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-lis…
5375 … DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag …
5401 … DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag …
5436 … DMA_CCR_ULEIE_Msk /*!< Update linked-list item error inter…
5451 #define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-lis…
5477 …k /*!< Source byte exchange within the unaligned half-word of each source w…
5497 … DMA_CTR1_DHX_Msk /*!< Destination half-word exchange */
5500 … DMA_CTR1_DWX_Msk /*!< Destination word-word exchange */
5589 … DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */
5743 #define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /*!< Chroma Sub-Samp…
6054 #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap …
6086 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet spe…
6095 … ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
6107 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit ma…
6131 #define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Pa…
6134 #define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Pa…
6154 #define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP …
6176 …wards all control frames except Pause packets to application even if they fail the Address Filter …
6179 …ARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter …
6282 #define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-…
6285 #define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
6291 #define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLA…
6316 #define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN …
6352 #define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN …
6388 #define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quan…
6498 #define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up …
6501 #define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FI…
6504 #define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Pa…
6510 #define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Pa…
6516 #define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Pa…
6524 /* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
6527 #define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet fi…
6585 #define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Vers…
6588 #define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined …
6642 …R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
6645 …0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
6648 …R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
6660 #define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Ti…
6672 #define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-u…
6684 #define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Suppo…
6728 #define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestam…
6951 #define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset…
7173 … ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
7176 … ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
7205 /* Bit definition for Ethernet MAC Sub-second Increment Register */
7208 #define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Incre…
7211 #define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond …
7221 #define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-second…
7234 #define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-secon…
7310 #define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timesta…
7315 #define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timesta…
7503 …MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
7506 … ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
7550 …QDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
7554 … ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deact…
7557 … ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activ…
7623 #define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned B…
8627 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
9025 #define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-match…
9028 #define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-match…
9426 …LASH_ECCSFADDR_SEC_FADD_Msk /*!< ECC single error correction fail address */
9431 …FLASH_ECCDFADDR_DED_FADD_Msk /*!< ECC double error detection fail address */
9511 …TE FLASH_NVSR_NVSTATE_Msk /*!< Non-volatile state */
9524 …ATE FLASH_NVSRP_NVSTATE_Msk /*!< Non-volatile state */
9667 … FLASH_OBW1SR_XSPI1_HSLV_Msk /*!< XSPI1 High-speed at low voltage …
9670 … FLASH_OBW1SR_XSPI2_HSLV_Msk /*!< XSPI2 High-speed at low voltage …
9682 … FLASH_OBW1SR_VDDIO_HSLV_Msk /*!< I/O High-speed at low voltage …
9701 … FLASH_OBW1SRP_XSPI1_HSLV_Msk /*!< XSPI1 High-speed at low voltage …
9704 … FLASH_OBW1SRP_XSPI2_HSLV_Msk /*!< XSPI2 High-speed at low voltage …
9713 … FLASH_OBW1SRP_VDDIO_HSLV_Msk /*!< I/O High-speed at low voltage …
9838 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!< Address-hold ph…
9845 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!< Data-phase dura…
9891 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!< Address-hold ph…
9898 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!< Data-phase dura…
9962 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!< Interrupt high-…
9971 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!< Interrupt high-…
10015 …MHIZ FMC_PMEM_MEMHIZ_Msk /*!< Common memory databus Hi-Z time */
10061 … FMC_PATT_ATTHIZ_Msk /*!< Attribute memory data bus Hi-Z time */
10127 #define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk /*!<Exit self-refres…
10183 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!< Number of auto-…
11712 /* Inter-integrated Circuit Interface (I2C) */
11798 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
11801 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
11830 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
11992 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
11997 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
12001 /* Improved Inter-integrated Circuit Interface (I3C) */
12013 #define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC …
12046 #define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keepe…
12201 …ER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */
12212 … /*!< Target Address Received during accepted IBI or Controller-role request */
12256 … I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */
12259 …DF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */
12327 … I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable…
12330 … I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt…
12386 …RF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */
12389 …F I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Fla…
12439 …R0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */
12466 … I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from…
12496 … I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */
12499 …GR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
12502 …C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C …
12579 …HOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */
12600 #define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-d…
12971 … LPTIM_ISR_CC1OF_Msk /*!< Capture/Compare 1 over-capture flag */
12974 … LPTIM_ISR_CC2OF_Msk /*!< Capture/Compare 2 over-capture flag */
13015 … LPTIM_ICR_CC1OCF_Msk /*!< Capture/Compare 1 over-capture clear flag */
13018 … LPTIM_ICR_CC2OCF_Msk /*!< Capture/Compare 2 over-capture clear flag */
13059 … LPTIM_DIER_CC1OIE_Msk /*!< Capture/Compare 1 over-capture interrupt ena…
13062 … LPTIM_DIER_CC2OIE_Msk /*!< Capture/Compare 2 over-capture interrupt ena…
13251 … MCE_CR_MKLOCK_Msk /*!< MCE master and fast master keys lock */
13259 #define MCE_SR_FMKVALID MCE_SR_FMKVALID_Msk /*!< MCE fast master…
13362 #define MCE_FMKEYR0_FMKEY MCE_FMKEYR0_FMKEY_Msk /*!< MCE fast maste…
13367 #define MCE_FMKEYR1_FMKEY MCE_FMKEYR1_FMKEY_Msk /*!< MCE fast maste…
13372 #define MCE_FMKEYR2_FMKEY MCE_FMKEYR2_FMKEY_Msk /*!< MCE fast maste…
13377 #define MCE_FMKEYR3_FMKEY MCE_FMKEYR3_FMKEY_Msk /*!< MCE fast maste…
13414 #define MCE_CCKEYR1_KEY MCE_CCKEYR1_KEY_Msk /*!< MCE fast maste…
13419 #define MCE_CCKEYR2_KEY MCE_CCKEYR2_KEY_Msk /*!< MCE fast maste…
13424 #define MCE_CCKEYR3_KEY MCE_CCKEYR3_KEY_Msk /*!< MCE fast maste…
13626 #define MDF_DFLTRSFR_HPFBYP MDF_DFLTRSFR_HPFBYP_Msk /*!< High-pass …
13629 … MDF_DFLTRSFR_HPFC_Msk /*!< High-pass filter cut-off frequency…
14319 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14320 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14323 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14326 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14327 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14328 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14329 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14330 #define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14331 #define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14332 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14333 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14334 #define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14335 #define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14338 #define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14339 #define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14340 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14341 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14344 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14345 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14346 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14347 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14348 #define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14349 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14350 #define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14351 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14352 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14353 #define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14356 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14357 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14358 #define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14361 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14362 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14363 #define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14364 #define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14365 #define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14366 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14367 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14368 #define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14371 #define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14374 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14375 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14376 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14377 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14378 #define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14379 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14380 #define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14381 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14382 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14383 #define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14384 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14385 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14388 #define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14389 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14390 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14391 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Ext…
14392 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Ext…
14395 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14396 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14397 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14398 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14399 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14400 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14401 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14402 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14403 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14404 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14405 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14406 #define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14407 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14410 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14413 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14414 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14415 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14416 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14417 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14418 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14419 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14422 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14425 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14426 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14427 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14428 #define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14431 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
14434 #define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14435 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14436 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14439 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14442 #define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14443 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14444 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14447 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14450 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14451 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14452 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14455 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14458 #define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14459 #define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14460 #define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14463 #define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14466 #define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14467 #define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14468 #define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14469 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14472 #define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14475 #define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14476 #define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14477 #define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14480 #define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14483 #define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14484 #define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14485 #define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14486 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14489 #define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14492 #define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14493 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14494 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14495 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14498 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
14501 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14502 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14503 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
14504 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14507 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
14510 #define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14511 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14512 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14513 #define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14514 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14515 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14516 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14517 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14518 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14519 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14522 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
14523 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
14524 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
14527 #define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14528 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14529 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14530 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14531 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14532 #define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14533 #define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14534 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14535 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14536 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14537 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14538 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14539 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
14542 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output…
14543 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output…
14544 #define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output…
14547 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< In…
14548 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< In…
14549 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< In…
14550 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< In…
14551 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< In…
14552 #define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< In…
14555 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output re…
14556 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output re…
14557 #define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output re…
14651 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up…
14728 #define PWR_CSR2_LDOEN PWR_CSR2_LDOEN_Msk /*!< Low Drop-Out r…
14732 #define PWR_CSR2_SDEN PWR_CSR2_SDEN_Msk /*!< SMPS Step-down …
14740 #define PWR_CSR2_SDHILEVEL PWR_CSR2_SDHILEVEL_Msk /*!< SMPS step-down…
14917 … PWR_APCR_PN7_PUPD_Msk /*!< Port N bit 7 pull-up/down configuration…
14921 … PWR_APCR_PO5_PUPD_Msk /*!< Port O bit 5 pull-up/down configuration…
14925 …PU PWR_APCR_I3CPB6_PU_Msk /*!< Port PB6 I3C pull-up bit configuration …
14929 …PU PWR_APCR_I3CPB7_PU_Msk /*!< Port PB7 I3C pull-up bit configuration …
14933 …PU PWR_APCR_I3CPB8_PU_Msk /*!< Port PB8 I3C pull-up bit configuration …
14937 …PU PWR_APCR_I3CPB9_PU_Msk /*!< Port PB9 I3C pull-up bit configuration …
14942 …PWR_PUCRN_PUN1 PWR_PUCRN_PUN1_Msk /*!< PUN1: Port N pull-up */
14946 …PWR_PUCRN_PUN6 PWR_PUCRN_PUN6_Msk /*!< PUN6: Port N pull-up */
14950 …WR_PUCRN_PUN12 PWR_PUCRN_PUN12_Msk /*!< PUN12: Port N pull-up */
14955 …R_PDCRN_PDN0 PWR_PDCRN_PDN0_Msk /*!< PDN0: Port N pull-down */
14959 …R_PDCRN_PDN1 PWR_PDCRN_PDN1_Msk /*!< PDN1: Port N pull-down */
14963 …PDN2N5 PWR_PDCRN_PDN2N5_Msk /*!< PDN2 to PDN5: Port N pull-down */
14967 …R_PDCRN_PDN6 PWR_PDCRN_PDN6_Msk /*!< PDN6: Port N pull-down */
14971 …DN8N11 PWR_PDCRN_PDN8N11_Msk /*!< PDN8 to PDN11: Port N pull-down */
14975 …_PDCRN_PDN12 PWR_PDCRN_PDN12_Msk /*!< PDN12: Port N pull-down */
14980 …PWR_PUCRO_PUO0 PWR_PUCRO_PUO0_Msk /*!< PUO0: Port O pull-up */
14984 …PWR_PUCRO_PUO1 PWR_PUCRO_PUO1_Msk /*!< PUO1: Port O pull-up */
14988 …PWR_PUCRO_PUO4 PWR_PUCRO_PUO4_Msk /*!< PUO4: Port O pull-up */
14993 …R_PDCRO_PDO0 PWR_PDCRO_PDO0_Msk /*!< PDO0: Port O pull-down */
14997 …R_PDCRO_PDO1 PWR_PDCRO_PDO1_Msk /*!< PDO1: Port O pull-down */
15001 …R_PDCRO_PDO2 PWR_PDCRO_PDO2_Msk /*!< PDO2: Port O pull-down */
15005 …R_PDCRO_PDO3 PWR_PDCRO_PDO3_Msk /*!< PDO3: Port O pull-down */
15009 …R_PDCRO_PDO4 PWR_PDCRO_PDO4_Msk /*!< PDO4: Port O pull-down */
15014 …DP0P3 PWR_PDCRP_PDP0P3_Msk /*!< PPO0 to PP03 : Port P pull-down */
15018 …DP4P7 PWR_PDCRP_PDP4P7_Msk /*!< PPO4 to PP07 : Port P pull-down */
15022 …P8P11 PWR_PDCRP_PDP8P11_Msk /*!< PPO8 to PP11 : Port P pull-down */
15026 …DP12P15 PWR_PDCRP_PDP12P15_Msk /*!< PP12 to PP15 : Port P pull-down */
15086 …FDATAH RAMECC_FDRH_FDATAH_Msk /* Failing data high (64-bit memory) */
17232 /* Real-Time Clock (RTC) */
17463 …_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
18420 …TVTOR SBS_BOOTSR_INITVTOR_Msk /*!< Initial vector for Cortex-M7 */
18479 …_IE_1 SBS_FPUIMR_FPU_IE_1_Msk /*!< Divide-by-zero Interrupt enabl…
18539 … SBS_CCVALR_NSRC_Msk /*!< NMOS transistors slew-rate compensation */
18542 … SBS_CCVALR_PSRC_Msk /*!< PMOS transistors slew-rate compensation */
18545 …BS_CCVALR_XSPI1_NSRC_Msk /*!< XSPIM_P1 NMOS transistors slew-rate compensation */
18548 …BS_CCVALR_XSPI1_PSRC_Msk /*!< XSPIM_P1 PMOS transistors slew-rate compensation */
18551 …BS_CCVALR_XSPI2_NSRC_Msk /*!< XSPIM_P2 NMOS transistors slew-rate compensation */
18554 …BS_CCVALR_XSPI2_PSRC_Msk /*!< XSPIM_P2 PMOS transistors slew-rate compensation */
18559 …BS_CCSWVALR_SW_NSRC_Msk /*!< Software NMOS transistors slew-rate compensation */
18562 …BS_CCSWVALR_SW_PSRC_Msk /*!< Software PMOS transistors slew-rate compensation */
18565 …LR_XSPI1_SW_NSRC_Msk /*!< XSPIM_P1 software NMOS transistors slew-rate compensation */
18568 …LR_XSPI1_SW_PSRC_Msk /*!< XSPIM_P1 software PMOS transistors slew-rate compensation */
18571 …LR_XSPI2_SW_NSRC_Msk /*!< XSPIM_P2 software NMOS transistors slew-rate compensation */
18574 …LR_XSPI2_SW_PSRC_Msk /*!< XSPIM_P2 software PMOS transistors slew-rate compensation */
18585 #define SBS_BKLOCKR_CM7LCKUP_BL SBS_BKLOCKR_CM7LCKUP_BL_Msk /*!< Cortex-M7…
18966 …k /*!< Boot acknowledgement received (boot acknowledgement check fail) */
19028 … /*!< Boot acknowledgement received (boot acknowledgement check fail) clear bit */
19102 … /*!< Boot acknowledgement received (boot acknowledgement check fail) interrupt enable */
19166 /* SPDIF-RX Interface */
19206 … SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchron…
19275 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error …
19382 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
19388 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC …
19460 …IDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
19548 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet a…
19551 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet s…
19566 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet a…
20497 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
20502 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload…
20775 …1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
20796 …2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
20811 /*----------------------------------------------------------------------------*/
20845 …3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
20866 …4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
20881 /*----------------------------------------------------------------------------*/
20910 …5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
20926 …6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
21019 …ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
21068 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
21084 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State S…
21087 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State S…
21114 …BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
21117 …K2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
21330 … UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC de…
21333 …2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC de…
21381 …D_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
21409 #define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast R…
21418 … UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to…
21421 … UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to…
21468 #define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swa…
21497 … UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected inter…
21528 #define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swa…
21569 #define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swa…
21598 … UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
21608 #define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive…
21640 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-p…
21643 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-p…
21646 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-p…
21649 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-p…
21652 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-…
21662 …LSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
21672 …SK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT han…
21720 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-d…
21758 …GDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
21820 … USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed …
21823 …_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
21826 …_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
21836 …YLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
21842 …GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
21979 …BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets r…
22347 … USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
22370 … USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator D…
22373 …S USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator D…
22668 …HAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
22947 …UP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets r…
23031 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - …
23040 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
23065 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - …
23085 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit…
23129 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate…
23132 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
23137 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-…
23151 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power…
23154 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Se…
23193 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
23250 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate…
23315 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate…
23318 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate…
23431 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
23446 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
24010 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
24178 /******************** UART Instances : Half-Duplex mode **********************/
24207 /******************** UART Instances : Wake-up from Stop mode **********************/