631   uint32_t tmpcr2;  in LL_TIM_HALLSENSOR_Init()  local
646   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in LL_TIM_HALLSENSOR_Init()
658   tmpcr2 |= TIM_CR2_TI1S;  in LL_TIM_HALLSENSOR_Init()
661   tmpcr2 |= LL_TIM_TRGO_OC2REF;  in LL_TIM_HALLSENSOR_Init()
684   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in LL_TIM_HALLSENSOR_Init()
815   uint32_t tmpcr2;  in OC1Config()  local
830   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC1Config()
861     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);  in OC1Config()
864     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);  in OC1Config()
868   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC1Config()
894   uint32_t tmpcr2;  in OC2Config()  local
909   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC2Config()
940     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);  in OC2Config()
943     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);  in OC2Config()
947   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC2Config()
973   uint32_t tmpcr2;  in OC3Config()  local
988   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC3Config()
1019     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);  in OC3Config()
1022     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);  in OC3Config()
1026   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC3Config()
1052   uint32_t tmpcr2;  in OC4Config()  local
1067   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);  in OC4Config()
1098     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);  in OC4Config()
1101     MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);  in OC4Config()
1105   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC4Config()