539   uint32_t tmpccer;  in LL_TIM_ENCODER_Init()  local
560   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
575   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_ENCODER_Init()
576   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);  in LL_TIM_ENCODER_Init()
577   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);  in LL_TIM_ENCODER_Init()
578   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
587   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
633   uint32_t tmpccer;  in LL_TIM_HALLSENSOR_Init()  local
652   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
679   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_HALLSENSOR_Init()
680   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);  in LL_TIM_HALLSENSOR_Init()
681   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
693   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
814   uint32_t tmpccer;  in OC1Config()  local
827   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
842   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);  in OC1Config()
845   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);  in OC1Config()
855     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);  in OC1Config()
858     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);  in OC1Config()
877   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
893   uint32_t tmpccer;  in OC2Config()  local
906   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
921   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);  in OC2Config()
924   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);  in OC2Config()
934     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);  in OC2Config()
937     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);  in OC2Config()
956   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
972   uint32_t tmpccer;  in OC3Config()  local
985   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
1000   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);  in OC3Config()
1003   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);  in OC3Config()
1013     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);  in OC3Config()
1016     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);  in OC3Config()
1035   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1051   uint32_t tmpccer;  in OC4Config()  local
1064   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1079   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);  in OC4Config()
1082   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);  in OC4Config()
1092     MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);  in OC4Config()
1095     MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);  in OC4Config()
1114   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1130   uint32_t tmpccer;  in OC5Config()  local
1144   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1153   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);  in OC5Config()
1156   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);  in OC5Config()
1175   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1191   uint32_t tmpccer;  in OC6Config()  local
1205   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1214   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);  in OC6Config()
1217   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);  in OC6Config()
1235   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()